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參數(shù)資料
| 型號： | AS7C31025-20TJI |
| 廠商： | ALLIANCE SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | Parallel-Load 8-Bit Shift Registers 16-SOIC -40 to 85 |
| 中文描述： | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封裝： | 0.300 INCH, SOJ-32 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 196K |
| 代理商： | AS7C31025-20TJI |
AS7C1025
AS7C31025
3/23/01; v.1.0
Alliance Semiconductor
P. 6 of 9
Data retention characteristics (over the operating range)
13
Parameter
Data retention waveform
AC test conditions
– 5V output load: see Figure B or Figure C.
– Input pulse level: GND to 3.0V See Figure A.
– Input rise and fall times: 2 ns. See Figure A.
– Input and output timing reference levels: 1.5V
Notes
1
2
3
4
5
6
7
8
9
10 CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 NA.
13 2V data retention applies to commercial temperature operating range only.
14 C=30pF, except all high Z and low Z parameters, where C=5pF.
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions
, Figures A, B, and C.
t
CLZ
and t
CHZ
are specified with CL = 5pF, as in Figure C. Transition is measured
±
500mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
Symbol
Test conditions
Min
Max
Unit
V
CC
for data retention
Data retention current
V
DR
I
CCDR
t
CDR
t
R
|
I
LI
|
V
CC
= 2.0V
CE
≥
V
CC
– 0.2V
V
IN
≥
V
CC
– 0.2V
or
V
IN
≤
0.2V
2.0
–
V
–
500
μA
Chip enable to data retention time
0
–
ns
Operation recovery time
t
RC
–
–
ns
Input leakage current
1
μA
V
CC
CE
t
R
t
CDR
Data retention mode
V
CC
V
CC
V
DR
≥
2.0V
V
IH
V
IH
V
DR
255W
C(14)
320W
D
OUT
GND
+3.3V
168W
Thevenin equivalent:
D
OUT
+1.728V (5V and 3.3V)
Figure C: 3.3V Output load
255W
C(14)
480W
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AS7C1025-20TJC | 128 x 64 pixel format, LED or EL Backlight available |
| AS7C31025-20TJC | 128 x 64 pixel format, LED or EL Backlight available |
| AS7C1025A | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-10JC | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C1025A-10TJC | 5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AS7C31025A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:5V/3.3V 128K x 8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025A-10JC | 制造商:Alliance Semiconductor 功能描述:SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 10ns 32-Pin SOJ |
| AS7C31025A-10JI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025A-10TC | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
| AS7C31025A-10TI | 制造商:ALSC 制造商全稱:Alliance Semiconductor Corporation 功能描述:5V/3.3V 128K X 8 CMOS SRAM (Revolutionary pinout) |
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