- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385099 > AM79Q031 (Electronic Theatre Controls, Inc.) Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79Q031 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices |
| 中文描述： | 四用戶線路音頻處理電路（QSLAC）設(shè)備 |
| 文件頁數(shù)： | 32/68頁 |
| 文件大?。?/td> | 1361K |
| 代理商： | AM79Q031 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁當(dāng)前第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
32
Am79Q02/021/031 Data Sheet
7. Transmit time slots and receive time slots are set to
0, 1, 2, and 3 for channels 1, 2, 3, and 4,
respectively. The clock slots are set to 0, with
transmit on the negative edge.
8. DXA port is selected for all channels.
9. DRA port is selected for all channels.
10. The master clock frequency selected is 8.192 MHz
and is programmed to come from PCLK.
11. All four channels are selected in the Channel
Enable register.
12. Any pending interrupts are cleared, all interrupts
are masked, and the Interrupt Output state is set to
open drain.
13. The supervision debounce time is set to 8 ms.
14. The previously programmed B, Z, X, R, GX, and
GR filters are unchanged.
15. The chopper clock frequency is set to 256 kHz but
the chopper clock is turned off.
16.The E1 Multiplex state is turned off and the polarity
is set for high going pulses.
17.No signalling on the PCM highway.
SIGNAL PROCESSING
Overview of Digital Filters
Several of the blocks in the signal processing section
are user programmable. These allow the user to
optimize the performance of the QSLAC device for the
system. Figure 12 shows the QSLAC device signal
processing and indicates the programmable blocks.
The advantages of digital filters are:
High reliability
No drift with time or temperature
Unit-to-unit repeatability
Superior transmission performance
Flexibility
Maximum possible bandwidth for V.34 modems
TSA
AR
AISN
Cutoff
Transmit
Path
(CTP)
Lower Receive
Gain (RG)
Full
Digital
Loop
back
(FDL)
GX
AX
TSA
Loopback
(TLB)
R
GR
X
ADC
Deci-
mator
DAC
LPF
& HPF
Com-
pressor
Ex-
pander
LPF
V
OUT
V
IN
TSA
B
Inter-
polator
Figure 12. QSLAC Device Block Diagram
+
+
+
Z
Digital
TX
Digital
RX
Inter-
polator
Deci-
mator
21108-027
High Pass Filter (HPF)
0
1 kHz Tone
(TON)
Cutoff Receive
Path (CRP)
VREF
*
*
*
*
*
*
*
*
*
programmable blocks
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79Q031JC | Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices |
| AMC1601B | CONTOUR DRAWING & BLOCK DIAGRAM |
| AMC2596 | 150 KHz, 3A STEP DOWN VOLTAGE REGULATOR |
| AMC2596-3.3 | 150 KHz, 3A STEP DOWN VOLTAGE REGULATOR |
| AMC2596-5.0 | 150 KHz, 3A STEP DOWN VOLTAGE REGULATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79Q031JC | 制造商:Advanced Micro Devices 功能描述: |
| AM79Q061JC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q061VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q063VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| AM79Q2241VC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。