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參數(shù)資料
| 型號(hào)： | AM79Q02JC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices |
| 中文描述： | 四用戶線路音頻處理電路（QSLAC）設(shè)備 |
| 文件頁數(shù)： | 41/68頁 |
| 文件大?。?/td> | 1361K |
| 代理商： | AM79Q02JC |
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SLAC Products
41
10, 11. Write/Read Transmit Clock Slot, Receive Clock Slot, and Transmit Clock Edge
MPI Command
(44/45h)
R/W = 0: Write
R/W = 1: Read
Transmit on A and B
TAB = 0*
Transmit data on highway selected by TPCM (See Commands 6,7
on page 40).
Transmit data on both highways A and B
TAB = 1
Transmit Edge
XE = 0*
XE = 1
Transmit changes on negative edge of PCLK
Transmit changes on positive edge of PCLK
Receive Clock Slot
RCS = 0*
–
7
Receive Clock Slot number
Transmit Clock Slot
TCS = 0*
–
7
Transmit Clock Slot number
The XE bit and the clock slots apply to all four channels; however, they cannot be written or read
unless at least one channel is selected in the Channel Enable Register.
* Power Up and Hardware Reset (
RST
) Value = 00h.
12, 13. Write/Read Configuration Register
(46/47h)
R/W = 0: Write
MPI Command
R/W = 1: Read
Interrupt Mode
INTM = 0
INTM = 1*
TTL-compatible output
Open drain output
Chopper Clock Control
CHP = 0*
CHP = 1
Chopper Clock is 256 kHz (2048/8 kHz)
Chopper Clock is 292.57 kHz (2048/7 kHz)
PCM Signaling Mode
SMODE = 0*
SMODE = 1
No signaling on PCM highway
Signaling on PCM highway
Clock Source Mode
CMODE = 0
CMODE = 1*
MCLK used as master clock; no E1 multiplexing allowed
PCLK used as master clock; E1 multiplexing allowed if enabled in
commands 49, 50.
The master clock frequency can be selected by CSEL. The master clock frequency selection
affects all channels.
D
7
0
TAB
D
6
1
XE
D
5
0
D
4
0
D
3
0
D
2
1
D
1
0
D
0
R/W
TCS0
Command
I/O Data
RCS2
RCS1
RCS0
TCS2
TCS1
D
7
0
D
6
1
CHP
D
5
0
D
4
0
D
3
0
D
2
1
D
1
1
D
0
R/W
CSEL0
Command
I/O Data
INTM
SMODE
CMODE
CSEL3
CSEL2
CSEL1
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