參數(shù)資料
型號(hào)： AM79Q02
廠商： Electronic Theatre Controls, Inc.
英文描述： Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
中文描述： 四用戶線路音頻處理電路（QSLAC）設(shè)備
文件頁(yè)數(shù)： 21/68頁(yè)
文件大?。?/td> 1361K
代理商： AM79Q02
SLAC Products
21
Master Clock
Auxiliary Output Clocks
Notes:
1. If CFAIL = 1 (Command 23), GX, GR, Z, B1, X, R, and B2 coefficients must not be written or read without first deactivating
all channels or switching them to default coefficients; otherwise, a chip select off time of 25
μ
s is required. If the low power
state (LPM = 1, Command 14) is selected and MCLK is also lost, this minimum chip select off time increases to 75
μ
s.
2. The first data bit is enabled on the falling edge of CS or on the falling edge of DCLK, whichever occurs last.
3. The PCM clock frequency must be an integer multiple of the frame sync frequency. The maximum allowable PCM clock
frequency is 8.192 MHz. The actual PCM clock rate is dependent on the number of channels allocated within a frame. The
minimum clock frequency is 128 kHz in Companded state and 256 kHz in Linear state, PCM Signaling state. The minimum
PCM clock rates should be doubled for parts with only one PCM highway in order to allow simultaneous access to all four
channels.
4. TSC is delayed from FS by a typical value of N
t
PCY
, where N is the value stored in the time/clock-slot register.
5. t
TSO
is defined as the time at which the output achieves the Open Circuit state.
6. There is a special conflict detection circuitry that will prevent high-power dissipation from occurring when the DXA or DXB
pins of two QSLAC devices are tied together and one QSLAC device starts to transmit before the other has gone into a
High-impedance state.
SWITCHING WAVEFORMS
Input and Output Waveforms for AC Tests
Master Clock Timing
No.
37
38
39
40
41
Symbol
A
MCY
t
MCR
t
MCF
t
MCH
t
MCL
Parameter
Min
–
100
Typ
Max
+100
15
15
Units
ppM
Note
Master clock accuracy
Rise time of clock
Fall time of clock
MCLK High pulse width
MCLK Low pulse width
ns
48
48
No.
Symbol
Parameter
Min
Typ
256
292.57
4.923
31.25
Max
Units
Note
42
f
CHP
Chopper clock frequency
CHP = 0
CHP = 1
kHz
43
44
f
E1
t
E1
E1 output frequency (CMODE = EE1 = 1)
E1 pulse width (CMODE = EE1 = 1)
μs
Test
Points
2.0
0.8
2.0
0.8
2.4
0.45
19256A-015
37
38
41
40
39
19256A-016
V
IH
V
IL
相關(guān)PDF資料
PDF描述
AM79Q021 Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
AM79Q021JC Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
AM79Q021VC Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
AM79Q02JC Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
AM79Q031 Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79Q021 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Quad Subscriber Line Audio-Processing Circuit (QSLAC) Devices
AM79Q021JC 制造商:Advanced Micro Devices 功能描述: 制造商:Advanced Micro Devices 功能描述:PCM CODEC, Quad, 44 Pin, Plastic, PLCC 制造商:Analog Devices 功能描述:PCM CODEC, Quad, 44 Pin, Plastic, PLCC
AM79Q021JC/T 制造商:Advanced Micro Devices 功能描述:
AM79Q021VC 制造商:Advanced Micro Devices 功能描述:
AM79Q02JC 制造商:Advanced Micro Devices 功能描述:
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