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參數(shù)資料
| 型號： | AM79C031JC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Advanced Subscriber Line Interface Circuit (ASLIC) Device |
| 中文描述： | 高級用戶線接口電路（ASLIC）設(shè)備 |
| 文件頁數(shù)： | 33/48頁 |
| 文件大?。?/td> | 501K |
| 代理商： | AM79C031JC |
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ASLIC/ASLAC Products
33
Master Clock
For 2.048 MHz ± 100 ppm, 4.096 MHz ± 100 ppm, or 8.192 MHz ± 100 ppm operation:
Notes:
1. DCLK may be stopped in the High or Low state indefinitely without loss of information.
2. The PCM clock (PCLK) frequency must be an integer multiple of the frame sync (FS) frequency with an accuracy of 800 ppm
relative to the MCLK frequency. This allowance includes any jitter that may occur between the PCM signals (FS, PCLK) and
MCLK. The actual PCLK rate is dependent on the number of channels allocated within a frame. The ASLAC device supports
2 to128 channels. The minimum clock frequency is 128 kHz. A PCLK of 1.544 MHz may be used for standard U.S. transmission
systems.
3. TSC is delayed from FS by a typical value of N
tPCY, where N is the value stored in the time/clock slot register.
4. t
TSO
is defined as the time at which the output driver turns off. The actual delay time is dependent on the load circuitry.
The maximum load capacitance on TSC is 150 pF and the minimum pullup resistance is 360
.
5. There is special circuitry that will prevent high-power dissipation from occurring when the DXA or DXB pins of two ASLAC
devices are tied together and one ASLAC device starts to transmit before the other has gone into a high-impedance state.
6. The first data bit is enabled on the falling edge of Chip Select or on the falling edge of DCLK, whichever occurs last. If chip
select is held Low for less than eight clocks, no command or data is accepted. If chip select is held Low for more than eight
clocks, the last 8 data bits are used as command or data.
7. The ASLAC device requires 40 cycles of the 8 MHz internal clock (5
μ
s) between SIO operations. If the MPI is being accessed
while the MCLK (or PCLK if in combined clock mode) input is not active, a Chip Select Off time of 20
μ
s is required.
Table 9. Master Clock
No.
Symbol
Parameter
Min.
Typ.
Max.
Units
Note
37
t
MCY
Master clock period (2.048 MHz)
488.23
488.28
488.33
ns
2
Master clock period (4.096 MHz)
244.11
244.14
244.17
ns
Master clock period (8.192 MHz)
122.05
122.07
122.09
ns
38
t
MCR
Rise time of clock
15
ns
39
t
MCF
Fall time of clock
15
ns
40
t
MCH
MCLK High pulse width
48
ns
41
t
MCL
MCLK Low pulse width
48
ns
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相關(guān)代理商/技術(shù)參數(shù) |
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| AM79C03AJC | 制造商:Advanced Micro Devices 功能描述:DATACOM, TIME SLOT ASSIGNER, 32 Pin Plastic PLCC |
| AM79C03AJC/T | 制造商:Advanced Micro Devices 功能描述:Electronic Component |
| AM79C03AJCT | 制造商:AMD 功能描述:NEW |
| AM79C03APC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:A-Law/u-Law CODEC |
| AM79C03JC | 制造商:Advanced Micro Devices 功能描述:Part Number Only |
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