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參數(shù)資料
| 型號(hào)： | AM29BDS640GTD4WSI |
| 廠商： | SPANSION LLC |
| 元件分類： | DRAM |
| 英文描述： | 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| 中文描述： | 4M X 16 FLASH 1.8V PROM, 14 ns, PBGA80 |
| 封裝： | 11 X 12 MM, 0.80 MM PITCH, FBGA-80 |
| 文件頁(yè)數(shù)： | 40/65頁(yè) |
| 文件大小： | 899K |
| 代理商： | AM29BDS640GTD4WSI |
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44
Am29BDS640G
October 31, 2002
AD V A NCE
INF O R M A T IO N
AC CHARACTERISTICS
Figure 17.
Reduced Wait-State Handshaking Burst Mode Read
Starting at an Odd Address
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
cycles to seven cycles. Clock is set for active rising edge.
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. This waveform represents a synchronous burst mode, the device will also operate in reduced wait-state handshaking under
a CLK synchronous burst mode.
Da
Da + 1
Da + n
OE#
DQ15-DQ0
A21-A0
Aa
AVD#
RDY
CLK
CE#
tCAS
tAAS
tAVC
tAVD
tAAH
tOE
tRACC
tOEZ
tCEZ
tIACC
tBDH
7 cycles for initial access shown.
Hi-Z
12
3
4
5
7
8
tRDYS
tBACC
tACC
6
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