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參數(shù)資料
| 型號(hào)： | AK5355VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Low Power 16bit ツヒ ADC |
| 中文描述： | 低功耗16位ADC的ツヒ |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大?。?/td> | 174K |
| 代理商： | AK5355VN |
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ASAHI KASEI
[AK5355]
MS0113-E-01
2005/01
- 11 -
Digital High Pass Filter
The AK5355 has a Digital High Pass Filter (HPF) to cancel DC-offset in both the ADC and input gain amplifier. The
cut-off frequency of the HPF is 3.4Hz at fs=44.1kHz. This cut-off frequency scales with the sampling frequency (fs).
Input Gain Amplifier
The AK5355 includes an input gain amplifier. The gain can be changed to 0dB or +15dB by using the SEL pin. Input
impedance is 40k
typically.
SEL pin
L
H
Table 2. Input Gain Amplifier
Power down
The AK5355 is placed in the power-down mode by bringing PDN “L”. The digital filter is also reset at the same time. This
reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. The
output data SDTO becomes available after 4128 cycles of LRCK clock. During initialization, the ADC digital data
outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle to the data corresponding to the
input signals at the end of initialization (Settling time equals the group delay time approximately).
Gain
0dB
+15dB
Normal Operation
Internal
State
PDN
Power-down
Initialize
Normal Operation
4128/fs(93.6ms@fs=44.1kHz)
Idle Noise
GD
GD
“0”data
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,BCLK
(1)
(2)
(3)
“0”data
Idle Noise
Notes:
(1) Digital output corresponding to the analog input is delayed by the Group Delay amount (GD).
(2) A/D output is “0” data in the power-down state.
(3) When the external clocks (MCLK, BCLK and LRCK) are stopped, the AK5355 should be placed in the
power-down state.
Figure 6. Power-down/up sequence example
System Reset
The AK5355 should be reset once by bringing PDN ”L” upon power-up. The AK5355 is powered up and the internal
timing starts clocking by LRCK “
↑
” after exiting reset and power down state by MCLK. The AK5355 is in the
power-down mode until MCLK and LRCK are input.
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PDF描述 |
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| AK5355 | LOW POWER 16BIT ADC |
| AK5355VT | LOW POWER 16BIT ADC |
| AK5357ET | 24Bit 96kHz ツヒ ADC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5355VNP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:16BIT AD + 15DB AMP |
| AK5355VT | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 16BIT ADC |
| AK5355VTP-E2 | 功能描述:IC ADC AUDIO STER 16BIT 16TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AK5356 | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 20BIT ADC WITH MIC AMP & PGA |
| AK5356VN | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 20BIT ADC WITH MIC AMP & PGA |
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