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參數(shù)資料
| 型號： | AK5353VT |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96kHz 24BIT ADC WITH SIGLE-ENDED INPUT |
| 中文描述： | 96kHz的24位ADC的與SIGLE端輸入 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 114K |
| 代理商： | AK5353VT |
ASAHI KASEI
[AK5353]
M0067-E-00
1999/06
- 9 -
SWITCHING CHARACTERISTICS (VA,VD=2.7
～
4.5V)
(Ta=25
°
C; VA,VD=2.7
～
4.5V; C
L
=20pF)
Parameter
Control Clock Frequency
Master Clock 256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
512fs:
Pulse Width Low
Pulse Width High
SCLK Frequency
LRCK Frequency
Serial Interface Timing
(Note 12)
SCLK Period
SCLK Pulse Width Low
Pulse Width High
LRCK Edge to SCLK
↑
(Note 13)
SCLK
↑
to LRCK Edge (Note 13)
LRCK Edge to SDTO Valid (Note 14)
SCLK
↓
to SDTO Valid
Power-Down & Reset Timing
PDN Pulse Width
PDN
↓
to SDTO delay (Note 15)
Symbol
min
typ
max
Units
fCLK
tCLKL
tCLKH
fCLK
fCLKL
fCLKH
fCLK
fCLKL
fCLKH
fSLK
fs
1.024
32
32
1.536
21
21
2.048
16
16
4
12.288
18.432
24.576
6.144
48
MHz
ns
ns
MHz
ns
ns
MHz
ns
ns
MHz
kHz
tSLK
tSLKL
tSLKH
tLRSH
tSHLR
tDLR
tDSS
160
65
65
30
30
50
50
ns
ns
ns
ns
ns
ns
ns
tPDW
tPDV
150
4129
ns
1/fs
Note:12. Refer to the operating overview section Serial Data Interface .
13. SCLK rising edge must not occur at the same time as LRCK edge.
14. In case of MSB justified format.
15. These cycles are the number of LRCK rising from PDN falling.
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