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參數(shù)資料
| 型號： | AK5353 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 96kHz ΔΣ 24bit ADC with Single-ended Input(帶寬采樣率4KHz到96KHz和單端輸入的24位立體聲ΔΣA/D轉(zhuǎn)換器) |
| 中文描述： | 96kHz的ΔΣADC的24位單端輸入（帶寬采樣率為4kHz到96kHz的和單端輸入的24位立體聲ΔΣA/數(shù)轉(zhuǎn)換器） |
| 文件頁數(shù)： | 13/17頁 |
| 文件大?。?/td> | 114K |
| 代理商： | AK5353 |
ASAHI KASEI
[AK5353]
M0067-E-00
1999/06
- 13 -
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Power down
The AK5353 is placed in the power-down mode by bringing PDN L and the digital filter is also reset at the same time.
This reset should always be done after power-up. In the power-down mode, the VREF and VCOM are AGND level. An
analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available
after 4129 cycles of LRCK clock. During initialization, the ADC digital data outputs of both channels are forced to a 2 s
complement 0 . The ADC outputs settle in the data corresponding to the input signals after the end of initialization
(Settling approximately takes the group delay time).
Normal Operation
Internal
State
PDN
Power-down
Initialize
Normal Operation
4129/fs(86.021ms@fs=48kHz)
Idle Noise
GD
GD
0 data
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(1)
(2)
(3)
0 data
Idle Noise
Notes:
(1) Digital output corresponding to analog input has the group delay (GD).
(2) A/D output is 0 data at the power-down state.
(3) When the external clocks (MCLK,SCLK,LRCK) are stopped, the AK5353 should be in the power-down state.
Figure 3. Power-down/up sequence example
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System Reset
The AK5353 should be reset once by bringing PDN L after power-up. The internal timing starts clocking by the rising
edge (falling edge at mode1) of LRCK upon exiting from reset.
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