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| 型號： | ADZS-BF548-EZLITE |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/100頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EZLITE ADZS-BF548 |
| 產(chǎn)品培訓(xùn)模塊： | Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services |
| 特色產(chǎn)品： | Blackfin? BF50x Series Processors |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Blackfin® |
| 類型： | DSP |
| 適用于相關(guān)產(chǎn)品： | ADSP-BF548 |
| 所含物品： | 板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 |
| 配用： | ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD ADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE |
| 相關(guān)產(chǎn)品： | ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGA ADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGA ADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGA ADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGA ADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGA ADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA ADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA ADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA ADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
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ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
Rev. C
|
Page 19 of 100
|
February 2010
A third-overtone crystal can be used at frequencies above
25 MHz. The circuit is then modified to ensure crystal operation
only at the third overtone by adding a tuned inductor circuit as
shown in Figure 7. A design procedure for third-overtone oper-
ation is discussed in detail in an Application Note, Using Third
Overtone Crystals (EE-168).
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 8 on Page 19, the core clock
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable 0.5
× to 64×
multiplication factor (bounded by specified minimum and max-
imum VCO frequencies). The default multiplier is 8
×, but it can
be modified by a software instruction sequence. This sequence
is managed by the bfrom_SysControl() function in the on-chip
ROM.
On-the-fly CCLK and SCLK frequency changes can be applied
by using the bfrom_SysControl() function in the on-chip ROM.
Whereas the maximum allowed CCLK and SCLK rates depend
on the applied voltages VDDINT and VDDEXT, the VCO is always
permitted to run up to the frequency specified by the part’s
speed grade.
The CLKOUT pin reflects the SCLK frequency to the off-chip
world. It functions as a reference for many timing specifications.
While inactive by default, it can be enabled using the
EBIU_AMGCTL register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 7 illustrates typical system clock ratios. The default
ratio is 4.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
dynamically changed without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. The default ratio is 1. This programmable core clock
capability is useful for fast core frequency modifications.
The maximum CCLK frequency not only depends on the part’s
speed grade, it also depends on the applied VDDINT voltage. See
Table 13 on Page 35 for details.
BOOTING MODES
The ADSP-BF54x Blackfin processors have many mechanisms
(listed in Table 9) for automatically loading internal and exter-
nal memory after a reset. The boot mode is specified by four
BMODE input pins dedicated to this purpose. There are two
categories of boot modes: master and slave. In master boot
Figure 7. External Crystal Connections
Note: For CCLK and SCLK specifications, see Table 16.
Figure 8. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
EN
CLKBUF
TO PLL CIRCUITRY
F R OVERTONE
OPERA
O
TION ONLY
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
18 pF*
EN
18 pF*
700
0
BLACKFIN
0
*
VDDEXT
1M
PLL
0.5x - 64x
1:15
1, 2, 4, 8
VCO
CLKIN
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
DYNAMIC MODIFICATION
ON-THE-FLY
CCLK
SCLK
Table 7. Example System Clock Ratios
Signal Name
SSEL3–0
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO
SCLK
0010
2:1
200
100
0110
6:1
300
50
1010
10:1
500
50
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
Divider Ratio
VCO/CCLK
Example Frequency Ratios
(MHz)
VCO
CCLK
00
1:1
300
01
2:1
300
150
10
4:1
500
125
11
8:1
200
25
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADZS-BF548-EZLITE | 制造商:Analog Devices 功能描述:Evaluation Kit |
| ADZS-BF548-MPSKIT | 功能描述:KIT STARTER MULTIMEDIA BF548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| ADZS-BF549-EZLITE | 功能描述:KIT EZLITE ADZS-BF549 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| ADZS-BF561-EZLITE | 功能描述:BOARD EVAL ADSP-BF561 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA |
| ADZS-BF561-MMSKIT | 功能描述:KIT STARTER MULTIMEDIA BF561 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
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