參數(shù)資料
型號: ADSP-BF533SKBC600
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: Blackfin Embedded Processor
中文描述: 16-BIT, 50 MHz, OTHER DSP, PBGA160
封裝: MO-205AE, CSBGA-160
文件頁數(shù): 27/56頁
文件大?。?/td> 671K
代理商: ADSP-BF533SKBC600
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
|
Page 27 of 56
|
March 2004
Parallel Peripheral Interface Timing
Table 20
and
Figure 15 on Page 27
describe Parallel Peripheral
Interface operations.
Table 20. Parallel Peripheral Interface Timing
Parameter
Timing Requirements
t
PCLKW
t
PCLK
t
SFSPE
t
HFSPE
t
SDRPE
t
HDRPE
Switching Characteristics - GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK
t
DDTPE
Transmit Data Delay After PPI_CLK
t
HDTPE
Transmit Data Hold After PPI_CLK
1
PPI_CLK frequency cannot exceed f
SCLK
/2
Min
Max
Unit
PPI_CLK Width
PPI_CLK Period
1
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
6.0
15.0
3.0
3.0
2.0
4.0
ns
ns
ns
ns
ns
ns
10.0
ns
ns
ns
ns
0.0
10.0
0.0
Figure 15. GP Output Mode and Frame Capture Timing
t
DDTPE
t
HDTPE
PPI_CLK
PPI_FS1
PPI_FS2
PPIx
DRIVE
EDGE
SAMPLE
EDGE
t
SFSPE
t
HFSPE
t
PCLKW
t
DFSPE
t
HOFSPE
t
SDRPE
t
HDRPE
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