參數(shù)資料
型號: ADSP-BF532SBBZ400
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: Blackfin Embedded Processor
中文描述: 16-BIT, 40 MHz, OTHER DSP, PBGA169
封裝: ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169
文件頁數(shù): 26/56頁
文件大小: 671K
代理商: ADSP-BF532SBBZ400
Rev. 0
|
Page 26 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
External Port Bus Request and Grant Cycle Timing
Table 19
and
Figure 14
describe external port bus request and
bus grant operations.
Table 19. External Port Bus Request and Grant Cycle Timing
Parameter
, 1, 2
Timing Requirements
t
BS
t
BH
Switching Characteristics
t
SD
t
SE
t
DBG
t
EBG
t
DBH
t
EBH
1
These are preliminary timing parameters that are based on worst-case operating conditions.
2
The pad loads for these timing parameters are 20 pF.
Min
Max
Unit
BR Asserted to CLKOUT High Setup
CLKOUT High to BR Deasserted Hold Time
4.6
0.0
ns
ns
CLKOUT Low to xMS, Address, and RD/WR disable
CLKOUT Low to xMS, Address, and RD/WR enable
CLKOUT High to BG High Setup
CLKOUT High to BG Deasserted Hold Time
CLKOUT High to BGH High Setup
CLKOUT High to BGH Deasserted Hold Time
4.5
4.5
3.6
3.6
3.6
3.6
ns
ns
ns
ns
ns
ns
Figure 14. External Port Bus Request and Grant Cycle Timing
ADDR19-1
ABE1-0
AMSx
CLKOUT
BG
AWE
ARE
BGH
BR
t
BH
t
BS
t
SD
t
SE
t
SD
t
SD
t
SE
t
SE
t
EBG
t
DBG
T
EBH
t
DBH
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