參數(shù)資料
型號： ADSP-BF532SBBC400
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： Blackfin Embedded Processor
中文描述： 16-BIT, 40 MHz, OTHER DSP, PBGA160
封裝： MO-205AE, CSBGA-160
文件頁數(shù)： 21/56頁
文件大小： 671K
代理商： ADSP-BF532SBBC400
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
|
Page 21 of 56
|
March 2004
TIMING SPECIFICATIONS
Table 10
through
Table 14
describe the timing requirements for
the ADSP-BF531/2/3 processor clocks. Take care in selecting
MSEL, SSEL, and CSEL ratios so as not to exceed the maximum
core clock and system clock as described in
Absolute Maximum
Ratings on Page 20
, and the Voltage Controlled Oscillator
(VCO) operating frequencies described in
Table 13
.
Table 13
describes Phase-Locked Loop operating conditions.
Table 10. Core and System Clock Requirements—ADSP-BF533SKBC600
Parameter
t
CCLK
t
CCLK
t
CCLK
t
CCLK
t
CCLK
t
SCLK
Min
1.67
2.10
2.35
2.66
4.00
Maximum of 7.5 or t
CCLK
Max
Unit
ns
ns
ns
ns
ns
ns
Core Cycle Period (V
DDINT
=1.2 V–5%)
Core Cycle Period (V
DDINT
=1.1 V–5%)
Core Cycle Period (V
DDINT
=1.0 V–5%)
Core Cycle Period (V
DDINT
=0.9 V–5%)
Core Cycle Period (V
DDINT
=0.8 V)
System Clock Period
Table 11. Core and System Clock Requirements—ADSP-BF533SBBC500 and ADSP-BF533SBBZ500
Parameter
t
CCLK
t
CCLK
t
CCLK
t
CCLK
t
CCLK
t
SCLK
Min
2.0
2.25
2.50
3.00
4.00
Maximum of 7.5 or t
CCLK
Max
Unit
ns
ns
ns
ns
ns
ns
Core Cycle Period (V
DDINT
=1.2 V–5%)
Core Cycle Period (V
DDINT
=1.1 V–5%)
Core Cycle Period (V
DDINT
=1.0 V–5%)
Core Cycle Period (V
DDINT
=0.9 V–5%)
Core Cycle Period (V
DDINT
=0.8 V)
System Clock Period
Table 12. Core and System Clock Requirements—ADSP-BF532/531 All Package Types
Parameter
t
CCLK
t
CCLK
t
CCLK
t
CCLK
t
CCLK
t
SCLK
Min
2.5
2.75
3.00
3.25
4.0
Maximum of 7.5 or t
CCLK
Max
Unit
ns
ns
ns
ns
ns
ns
Core Cycle Period (V
DDINT
=1.2 V–5%)
Core Cycle Period (V
DDINT
=1.1 V–5%)
Core Cycle Period (V
DDINT
=1.0 V–5%)
Core Cycle Period (V
DDINT
=0.9 V–5%)
Core Cycle Period (V
DDINT
=0.8 V)
System Clock Period
Table 13. Phase-Locked Loop Operating Conditions
Parameter
f
VCO
Min
50
Max
Max CCLK
Unit
MHz
Voltage Controlled Oscillator (VCO) Frequency
Table 14. Maximum SCLK Conditions
Parameter
Condition
V
DDEXT
= 3.3 V
V
DDEXT
= 2.5 V
Unit
MBGA
f
SCLK
f
SCLK
LQFP
f
SCLK
f
SCLK
1
Set bit 7 (output delay) of PLL_CTL register.
V
DDINT
>=
1.14 V
V
DDINT
<
1.14 V
133
100
133
100
MHz
MHz
V
DDINT
>=
1.14 V
V
DDINT
<
1.14 V
133
83
133
1
83
1
MHz
MHz
相關(guān)PDF資料
PDF描述
ADSP-BF532SBBZ400 Blackfin Embedded Processor
ADSP-BF532SBST400 28-2 (14 Contacts) Pin Insert; For Use With:Amphenol MIL-C-5015 97 Series Circular Connectors; No. of Contacts:14; Gender:Male; Operating Voltage:1250V
ADSP-BF533 Blackfin Embedded Processor
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