參數(shù)資料
型號: ADSP-BF532
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: Blackfin Embedded Processor
中文描述: Blackfin嵌入式處理器
文件頁數(shù): 37/56頁
文件大?。?/td> 671K
代理商: ADSP-BF532
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
|
Page 37 of 56
|
March 2004
Timer Cycle Timing
Table 30
and
Figure 23
describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of f
SCLK
/2 MHz.
Table 30. Timer Cycle Timing
Parameter
Timing Characteristics
t
WL
t
WH
Switching Characteristics
t
HTO
1
The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2
The minimum time for t
HTO
is one cycle, and the maximum time for t
HTO
equals (2
–1) cycles.
Min
Max
Unit
Timer Pulse Width Input Low
1
(Measured in SCLK Cycles)
Timer Pulse Width Input High
1
(Measured in SCLK Cycles)
1
1
SCLK
SCLK
Timer Pulse Width Output
2
(Measured in SCLK Cycles)
1
(2
32
–1)
SCLK
Figure 23. Timer PWM_OUT Cycle Timing
CLKOUT
TMRx
(PWM OUTPUT MODE)
t
HTO
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
t
WL
t
WH
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