參數(shù)資料
型號: ADSP-BF532
廠商: Analog Devices, Inc.
元件分類: 數(shù)字信號處理
英文描述: Blackfin Embedded Processor
中文描述: Blackfin嵌入式處理器
文件頁數(shù): 33/56頁
文件大?。?/td> 671K
代理商: ADSP-BF532
ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. 0
|
Page 33 of 56
|
March 2004
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 27
and
Figure 19
describe SPI port master operations.
Table 27. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t
SSPIDM
t
HSPIDM
Switching Characteristics
t
SDSCIM
t
SPICHM
t
SPICLM
t
SPICLK
t
HDSM
t
SPITDM
t
DDSPIDM
t
HDSPIDM
Min
Max
Unit
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
7.5
–1.5
ns
ns
SPISELx Low to First SCK edge (x=0 or 1)
Serial Clock High period
Serial Clock Low period
Serial Clock Period
Last SCK Edge to SPISELx High (x=0 or 1)
Sequential Transfer Delay
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
0
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
6
4.0
Figure 19. Serial Peripheral Interface (SPI) Port—Master Timing
t
SSPIDM
t
HSPIDM
t
HDSPIDM
LSB
MSB
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
SPISELx
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
t
SPICHM
t
SPICLM
t
SPICLM
t
SPICLK
t
SPICHM
t
HDSM
t
SPITDM
t
HDSPIDM
LSB VALID
LSB
MSB
MSB VALID
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
t
SSPIDM
CPHA=1
CPHA=0
MSB VALID
t
SDSCIM
t
SSPIDM
LSB VALID
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