參數(shù)資料
型號: ADSP-BF531SBBZ400
廠商: ANALOG DEVICES INC
元件分類: 數(shù)字信號處理
英文描述: Blackfin Embedded Processor
中文描述: 16-BIT, 40 MHz, OTHER DSP, PBGA169
封裝: ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169
文件頁數(shù): 34/56頁
文件大?。?/td> 671K
代理商: ADSP-BF531SBBZ400
Rev. 0
|
Page 34 of 56
|
March 2004
ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port
—Slave Timing
Table 28
and
Figure 20
describe SPI port slave operations.
Table 28. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
SPICHS
t
SPICLS
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
t
SSPID
t
HSPID
Switching Characteristics
t
DSOE
t
DSDHI
t
DDSPID
t
HDSPID
Min
Max
Unit
Serial Clock High Period
Serial Clock low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
2t
SCLK
–1.5
2t
SCLK
–1.5
4t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
2t
SCLK
–1.5
1.6
1.6
ns
ns
ns
ns
ns
ns
ns
ns
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
0
0
0
0
8
8
10
10
ns
ns
ns
ns
Figure 20. Serial Peripheral Interface (SPI) Port—Slave Timing
t
HSPID
t
DDSPID
t
DSDHI
LSB
MSB
MSB VALID
t
HSPID
t
DSOE
t
DDSPID
t
HDSPID
MISO
(OUTPUT)
MOSI
(INPUT)
t
SSPID
SPISS
(INPUT)
SCK
(CPOL = 0)
(INPUT)
SCK
(CPOL = 1)
(INPUT)
t
SDSCI
t
SPICHS
t
SPICLS
t
SPICLS
t
SPICLK
t
HDS
t
SPICHS
t
SSPID
t
HSPID
t
DSDHI
LSB VALID
MSB
MSB VALID
t
DSOE
t
DDSPID
MISO
(OUTPUT)
MOSI
(INPUT)
t
SSPID
LSB VALID
LSB
CPHA=1
CPHA=0
t
SPITDS
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