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參數(shù)資料
| 型號： | ADS8364Y/2K |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 12/26頁 |
| 文件大小： | 0K |
| 描述： | IC ADC LP 16BIT 250KSPS 64-TQFP |
| 產(chǎn)品培訓模塊： | Data Converter Basics |
| 標準包裝： | 2,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 6 |
| 功率耗散（最大）： | 471.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP |
| 供應商設備封裝： | 64-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 12 個單端，雙極；6 個差分，雙極 |
| 配用： | 296-30708-ND - EVAL MODULE FOR ADS8364 ADS8364EVM-ND - EVALUATION MODULE FOR BQ2018 |
ADS8364
2
SBAS219C
www.ti.com
MAXIMUM
INTEGRAL
NO MISSING
SPECIFIED
LINEARITY
CODES
PACKAGE
TEMPERATURE
ORDERING
TRANSPORT
PRODUCT
ERROR (LSB)
PACKAGE-LEAD
DESIGNATOR
RANGE
NUMBER
MEDIA, QUANTITY
ADS8364Y
±8
14
TQFP-64
PAG
–40
°C to +85°C
ADS8364Y/250
Tape and Reel, 250
""
"
ADS8364Y/2K
Tape and Reel, 2000
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com.
PACKAGE/ORDERING INFORMATION(1)
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings over operating free-air temperature (unless
otherwise noted)(1)
Supply Voltage, AGND to AVDD ............................................................... –0.3V to 6V
Supply Voltage, BGND to BVDD ............................................................... –0.3V to 6V
Supply Voltage, DGND to DVDD .............................................................. –0.3V to 6V
Analog Input Voltage Range ..................... AGND – 0.3V to AVDD + 0.3V
Reference Input Voltage ........................... AGND – 0.3V to AVDD + 0.3V
Digital Input Voltage Range ...................... BGND – 0.3V to BVDD + 0.3V
Ground Voltage Differences, AGND to BGND/DGND .....................
±0.3V
Voltage Differences, BVDD, DVDD to AGND .......................... –0.3V to 6V
Input Current ot Any Pin Except Supply ......................... –20mA to 20mA
Power Dissipation ....................................... See Dissipation Rating Table
Operating Virtual Junction Temperature Range, TJ ........ –40°C to 150°C
Operating Free-Air Temperature Range, TA ...................... –40°C to 85°C
Storage Temperature Range, TSTG .................................. –65°C to 150°C
Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260
°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
NOTE: (1) Stresses beyond those listed under
Absolute Maximum Ratings may
cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under
Recommended Operating Conditions is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Supply Voltage, AGND to AVDD
4.75
5
5.25
V
Supply Voltage, BGND to BVDD
Low-Voltage Levels
2.7
3.6
V
5V Logic Levels
4.5
5
5.5
V
Supply Voltage, DGND to DVDD
4.75
5
5.25
V
Difference AVDD to DVDD
–0.3
0
0.3
V
Reference Input Voltage
1.5
2.5
2.6
V
Operating Common-Mode Signal
–IN
2.2
2.5
2.8
V
Analog Inputs
+IN – (–IN)
0
±V
REF
V
Operating Junction Temperature Range, TJ
–40
125
°C
DERATING
FACTOR
TA ≤ +25°CTA = +70°CTA = +85°C
ABOVE
POWER
BOARD
PACKAGE
RθJC
RθJA
TA = +25°C
RATING
Low-K(1)
PAG
8.6
°C/W
68.5
°C/W
14.598mW/
°C
1824mW
1168mW
949mW
High-K(2)
PAG
8.6
°C/W
42.8
°C/W
23.364mw/
°C
2920mW
1869mW
1519mW
NOTES: (1) The JEDEC Low K (1s) board design used to derive this data was a 3-inch x 3-inch, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC High K (2s2p) board design used to derive this data was a 3-inch x 3-inch, multilayer board with 1-ounce internal power and ground planes and 2-ounce
copper traces on the top and bottom of the board.
PACKAGE DISSIPATION RATING TABLE
R
ON = 20
C
(SAMPLE) = 20pF
BV
DD
D
IN
BGND
AV
DD
A
IN
AGND
Diode Turn-on Voltage: 0.35V
Equivalent Digital Input Circuit
Equivalent Analog Input Circuit
EQUIVALENT INPUT CIRCUIT
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