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參數(shù)資料
| 型號： | AD9956YCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER 1.8V 48LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 3GHz |
| 調(diào)節(jié)字寬（位）： | 48 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9956-VCO/PCBZ-ND - BOARD EVAL 14BIT 1.8V 48LFCSP AD9956/PCBZ-ND - BOARD EVAL FOR AD9956 |
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AD9956
Rev. A | Page 22 of 32
SERIAL PORT OPERATION
An AD9956 serial data-port communication cycle has two
phases. Phase 1 is the instruction cycle, which is the writing of
an instruction byte to the AD9956, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9956 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the
register being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9956. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9956
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing Control
Function Register 2, which is four bytes wide, Phase 2 requires that
four bytes be transferred. If accessing a frequency tuning word,
which is six bytes wide, Phase 2 requires that six bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9956
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9956 is registered on the rising edge of
SCLK. All data is driven out of the AD9956 on the falling edge
of SCLK. Figure 29 through Figure 32 are useful in understand-
ing the general operation of the AD9956 serial port.
04806-0-004
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 29. Serial Port Write Timing—Clock Stall Low
04806-0-005
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
DO 5 DO 4 DO 3 DO 2 DO 1
DO 0
DO 7
DO 6
SDO
CS
Figure 30. 3-Wire Serial Port Read Timing—Clock Stall Low
04806-0-006
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 31. Serial Port Write Timing—Clock Stall High
04806-0-007
I6
I5
I4
I3
I2
I1
DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
I0
DO 7 DO 6
I7
INSTRUCTION CYCLE
SCLK
SDI/O
DATA TRANSFER CYCLE
CS
Figure 32. 2-Wire Serial Port Read Timing—Clock Stall High
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