參數(shù)資料
型號(hào): AD9943KCPZ
廠商: Analog Devices Inc
文件頁數(shù): 5/20頁
文件大?。?/td> 0K
描述: IC CCD SIGNAL PROCESSOR 32-LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: CCD 信號(hào)處理器,10 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 托盤
Data Sheet
AD9943/AD9944
SERIAL INTERFACE
Figure 10. Serial Write Operation
Figure 11. Continuous Serial Write Operation to All Registers
tLS
tLH
SDATA
SCK
SL
TEST BIT
A2
0
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tDS
tDH
NOTES
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
3. ALL 12 DATA BITS D0–D11 MUST BE WRITTEN. IF THE REGISTER CONTAINS FEWER THAN 12 BITS, ZEROS SHOULD BE USED
FOR THE UNDEFINED BITS.
4. TEST BIT IS FOR INTERNAL USE ONLY AND MUST BE SET LOW.
D11
02905-B-011
SDATA
A0
A1
A2
D0
D1
D2
D3
D4
D5
D10
D11
SCK
SL
0
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 12-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 12-BIT DATA-WORD. (ALL 12 BITS MUST BE WRITTEN.)
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED AT THE NEXT SL RISING EDGE.
D0
D1
D10
D11
D0
...
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
D2
D1
...
1
16
2
3
4
5
6
7
8
9
10
15
18
17
28
27
30
29
31
TEST
BIT
02905-B-012
Rev. C | Page 13 of 20
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