參數(shù)資料
型號: AD9552/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 23/32頁
文件大小: 0K
描述: BOARD EVALUATION FOR AD9552
設計資源: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
AD9552 Schematics
AD9552 Layout
標準包裝: 1
主要目的: 計時,時鐘發(fā)生器
嵌入式:
已用 IC / 零件: AD9552
主要屬性: 6.6 MHz ~ 112.5 MHz 輸入
次要屬性: CMOS,LVPECL 和 LVDS 兼容
已供物品:
Data Sheet
AD9552
Rev. E | Page 3 of 32
SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 3.3 V; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
3.135
3.30
3.465
V
Pin 7, Pin 18, Pin 21, Pin 28
POWER CONSUMPTION
Total Current
149
169
mA
At maximum output frequency with both output channels active
VDD Current By Pin
Pin 7
2
3
mA
Pin 18
77
86
mA
Pin 21
35
41
mA
Pin 28
35
41
mA
LVPECL Output Driver
36
41
mA
900 MHz with 100 Ω termination between both pins of the output
driver
LOGIC INPUT PINS
INPUT CHARACTERISTICS1
Logic 1 Voltage, V
IH
1.0
V
For the CMOS inputs, a static Logic 1 results from either a pull-up
resistor or no connection
Logic 0 Voltage, V
IL
0.8
V
Logic 1 Current, I
IH
3
A
Logic 0 Current, I
IL
17
A
LOGIC OUTPUT PINS
Output Characteristics
Output Voltage High, V
OH
2.7
V
Output Voltage Low, V
OL
0.4
V
RESET PIN
Input Characteristics2
Input Voltage High, V
IH
1.8
V
Input Voltage Low, V
IL
1.3
V
Input Current High, I
INH
0.3
12.5
A
Input Current Low, I
INL
31
43
A
Minimum Pulse Width High
2
ns
REFERENCE CLOCK
INPUT CHARACTERISTICS
Frequency Range
7.94
MHz
N3 = 255; 2× frequency multiplier enabled; valid for all VCO bands
6.57
MHz
N3 = 255; 2× frequency multiplier enabled; f
VCO = 3.35 GHz, which con-
strains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz
(that is, f
OUT1 = 3.35 ÷ M GHz, where M is the product of the P0 and P1
output divider values)
93.06
MHz
SDM4 disabled; N3 = 365; valid for all VCO bands
71.28
MHz
SDM4 enabled; N3 = 476; valid for all VCO bands
112.5
MHz
SDM4 disabled; N3 = 365; f
VCO = 4.05 GHz, which constrains the
frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is,
f
OUT1 = 4.05÷M GHz, where M is the product of the P0 and P1 output
divider values)
86.17
MHz
VCO = 4.05 GHz, which constrains the frequency
at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, f
OUT1 =
4.05÷M GHz, where M is the product of the P
0 and P1 output divider
values)
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