參數(shù)資料
型號(hào): ISL12028AIV27Z-T
廠商: Intersil
文件頁(yè)數(shù): 19/29頁(yè)
文件大?。?/td> 0K
描述: IC RTC/CALENDAR EEPROM 14TSSOP
產(chǎn)品培訓(xùn)模塊: Solutions for Industrial Control Applications
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘/日歷
特點(diǎn): 警報(bào)器,閏年,監(jiān)控器,監(jiān)視計(jì)時(shí)器
時(shí)間格式: HH:MM:SS(12/24 小時(shí))
數(shù)據(jù)格式: YY-MM-DD-dd
接口: I²C,2 線串口
電源電壓: 2.7 V ~ 5.5 V
電壓 - 電源,電池: 1.8 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 14-TSSOP
包裝: 帶卷 (TR)
26
FN8233.9
November 30, 2010
.
Alarm Operation Examples
Following, are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm 0 set with single interrupt (IM = ”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm 0 registers as follows:
B. Also the AL0E bit must be set as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1” and also bringing the IRQ/FOUT output
low.
VRESET(2.63V)
RESET
VTRIP
VDD
tPURST
(2.2V)
IBAT
(BATTERY BACKUP MODE)
(VDD POWER, VBAT NOT CONNECTED)
FIGURE 29. EXAMPLE RESET OPERATION IN MODE A OR C
VBAT(3.0V)
I2C-BUS ACTIVE
VRESET (2.63V)
RESET
VTRIP
VDD
(2.2V)
IBAT
(BATTERY BACKUP MODE)
FIGURE 30. RESET OPERATION IN MODE D
VBAT (3.0V)
I2C-BUS ACTIVE
tPURST
ALARM0
REGISTER
BIT
DESCRIPTION
76
543210
HEX
SCA0
00
000000
00h
Seconds disabled
MNA0
10
110000
B0h Minutes set to 30,
enabled
HRA0
1
0
010001
91h
Hours set to 11,
enabled
DTA0
10
000001
81h
Date set to 1,
enabled
MOA0
1
0000001
81h
Month set to 1,
enabled
DWA0
0
0000000
00h
Day of week
disabled
CONTROL
REGISTER
BIT
DESCRIPTION
765
43210
HEX
INT
001
00000
x0hEnable Alarm
ALARM0
REGISTER
BIT
DESCRIPTION
7
6543210
HEX
ISL12028, ISL12028A
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