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參數(shù)資料
| 型號： | MAX7325AEG+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 11/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 24QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 接口： | I²C |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 頻率 - 時鐘： | 400kHz |
| 電源電壓： | 1.71 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-QSOP |
| 包裝： | 管件 |
| 包括： | POR |
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
3
Maxim Integrated
PORT AND INTERRUPT
INT TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Port Output Data Valid
tPPV
CL
≤ 100pF
4
s
Port Input Setup Time
tPSU
CL
≤ 100pF
0
s
Port Input Hold Time
tPH
CL
≤ 100pF
4
s
INT Input Data Valid Time
tIV
CL
≤ 100pF
4
s
INT Reset Delay Time from STOP
tIP
CL
≤ 100pF
4
s
INT Reset Delay Time from
Acknowledge
tIR
CL
≤ 100pF
4
s
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
s
Hold Time (Repeated) START
Condition
tHD, STA
0.6
s
Repeated START Condition
Setup Time
tSU, STA
0.6
s
STOP Condition Setup Time
tSU, STO
0.6
s
Data Hold Time
tHD, DAT
(Note 2)
0.9
s
Data Setup Time
tSU, DAT
100
ns
SCL Clock Low Period
tLOW
1.3
s
SCL Clock High Period
tHIGH
0.7
s
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 3, 4)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 3, 4)
20 +
0.1Cb
300
ns
Fall Time of SDA Transmitting
tF,TX
(Notes 3, 4)
20 +
0.1Cb
250
ns
Pulse Width of Spike Suppressed
tSP
(Note 5)
50
ns
Capacitive Load for Each Bus
Line
Cb
(Note 3)
400
pF
RST Pulse Width
tW
500
ns
RST Rising to START Condition
Setup Time
tRST
1s
Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 x V+ and 0.7 x V+.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
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