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參數(shù)資料
| 型號： | PIC18F2221T-I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 14/110頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 2KX16 28SOIC |
| 標準包裝： | 1,600 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 25 |
| 程序存儲器容量： | 4KB（2K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 256 x 8 |
| RAM 容量： | 512 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
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2007 Microchip Technology Inc.
DS41232D-page 109
PIC12F635/PIC16F636/639
11.22 Low-Current Sleep Mode
The Sleep command from the microcontroller, via an
SPI Interface command, places the AFE into an ultra
Low-current mode. All circuits including the RF Limiter,
except the minimum circuitry required to retain register
memory and SPI capability, will be powered down to
minimize the AFE current draw. Power-on Reset or any
SPI command, other than Sleep command, is required
to wake the AFE from Sleep.
11.23 Low-Current Standby Mode
The AFE is in Standby mode when no LF signal is
present on the antenna inputs but the AFE is powered
and ready to receive any incoming signals.
11.24 Low-Current Operating Mode
The AFE is in Low-current Operating mode when a LF
signal is present on an LF antenna input and internal
circuitry is switching with the received data.
11.25 Error Detection of AFE
Configuration Register Data
The AFE’s Configuration registers are volatile memory.
Therefore, the contents of the registers can be
corrupted or cleared by any electrical incidence such
as battery disconnect. To ensure the data integrity, the
AFE has an error detection mechanism using row and
column parity bits of the Configuration register memory
map. The bit 0 of each register is a row parity bit which
is calculated over the eight Configuration bits (from bit
1 to bit 8). The Column Parity Register (Configuration
Register 6) holds column parity bits; each bit is
calculated over the respective columns (Configuration
registers 0 to 5) of the Configuration bits. The STATUS
register is not included for the column parity bit
calculation. Parity is to be odd. The parity bit set or
cleared makes an odd number of set bits. The user
needs to calculate the row and column parity bits using
the contents of the registers and program them. During
operation, the AFE continuously calculates the row and
column parity bits of the configuration memory map. If
a parity error occurs, the AFE lowers the SCLK/ALERT
pin (interrupting the microcontroller section) indicating
the configuration memory has been corrupted or
unloaded and needs to be reprogrammed.
At an initial condition after a Power-On-Reset, the
values of the registers are all clear (default condition).
Therefore, the AFE will issue the parity bit error by
lowering the SCLK/ALERT pin. If user reprograms the
registers with correct parity bits, the SCLK/ALERT pin
will be toggled to logic high level immediately.
The parity bit errors do not change or affect the AFE’s
functional operation.
Table 11-4 shows an example of the register values
and corresponding parity bits.
TABLE 11-4:
AFE CONFIGURATION REGISTER PARITY BIT EXAMPLE
Register Name
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Row Parity)
Configuration Register 01
0
1
0
1
0
0
Configuration Register 1
00
0
1
Configuration Register 2
00
0
1
Configuration Register 3
00
0
1
Configuration Register 4
00
0
1
Configuration Register 5
10
0
0
Configuration Register 6
(Column Parity Register)
11
0
1
0
1
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