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參數(shù)資料
| 型號： | AD7988-1BCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SRL 100KSPS 10LFCSP |
| 標準包裝： | 5,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
Data Sheet
AD7988-1/AD7988-5
Rev. D | Page 19 of 24
CS MODE 4-WIRE
This mode is typically used when multiple AD7988-x devices
are connected to an SPI-compatible digital host.
A connection diagram example using two AD7988-x devices is
shown in Figure 36, and the corresponding timing is given in
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion time.
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7988-x
can be read.
DIGITAL HOST
CONVERT
CLK
DATA IN
AD7988-1/
AD7988-5
SDO
CNV
SCK
AD7988-1/
AD7988-5
SDO
CNV
SCK
CS1
CS2
SDI
10231-
037
Figure 36. 4-Wire CS Mode Connection Diagram
tCONV
tCYC
ACQUISITION
tACQ
tSCK
tSCKH
tSCKL
CONVERSION
SCK
CNV
tSSDICNV
tHSDICNV
SDO
D15
D13
D14
D1
D0
D15
D14
D1
D0
tHSDO
tEN
1
2
3
14
15
16
17
18
30
31
32
tDSDO
tDIS
SDI (CS1)
SDI (CS2)
10231-
038
Figure 37. 4-Wire CS Mode Serial Interface Timing
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