參數(shù)資料
型號: AD797BN
廠商: ANALOG DEVICES INC
元件分類: 運(yùn)動控制電子
英文描述: Ultralow Distortion, Ultralow Noise Op Amp
中文描述: OP-AMP, 60 uV OFFSET-MAX, 110 MHz BAND WIDTH, PDIP8
封裝: MINI, PLASTIC, DIP-8
文件頁數(shù): 11/16頁
文件大?。?/td> 406K
代理商: AD797BN
AD797
REV. C
–11–
600
100
20–120pF
AD797
**
2
7
3
4
6
**
V
OUT
–V
S
+V
S
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
I
IN
R
S
*
C
S
*
R1
Figure 36. I-to-V Converter Connection
greater than 33 pF a 100
series resistor is required. A by-
passed balancing resistor (R
S
and C
S
) can be included to mini-
mize dc errors.
T HE INVE RT ING CONFIGURAT ION
T he inverting configuration (Figure 37) presents a low input
impedance, R1, to the source. For this reason, the goals of both
low noise and input buffering are at odds with one another.
Nonetheless, the excellent dynamics of the AD797 will make it
the preferred choice in many inverting applications, and with care-
ful selection of feedback resistors the noise penalties will be mini-
mal. Some examples are presented in T able II and Figure 37.
R
L
C
L
V
IN
AD797
**
2
7
3
4
6
**
V
OUT
–V
S
+V
S
* SEE TEXT
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
R
S
*
R2
R1
Figure 37. Inverting Amplifier Connection
T able III. Values for Inverting Circuit
Noise
(E xcluding r
S
)
Gain
R1
R2
C
L
–1
–1
–10
1 k
300
150
1 k
300
1500
20 pF
10 pF
5 pF
3.0 nV/
Hz
1.8 nV/
Hz
1.8 nV/
Hz
DRIVING CAPACIT IVE LOADS
T he capacitive load driving capabilities of the AD797 are dis-
played in Figure 38. At gains over 10 usually no special precau-
tions are necessary. If more drive is desirable the circuit in
Figure 39 should be used. Here a 5000 pF load can be driven
cleanly at any noise gain
2.
100nF
10nF
1pF
1
10
CLOSED-LOOP GAIN
1k
100
1nF
100pF
10pF
C
Figure 38. Capacitive Load Drive Capability vs. Closed
Loop Gain
100
1k
C1
1k
20pF
33
V
IN
AD797
**
2
7
3
4
6
**
V
OUT
–V
S
+V
S
** USE POWER SUPPLY BYPASSING SHOWN IN FIGURE 32.
200pF
Figure 39. Recommended Circuit for Driving a High
Capacitance Load
SE T T LING T IME
T he AD797 is unique among ultralow noise amplifiers in that it
settles to 16 bits (<150
μ
V) in less than 800 ns. Measuring this
performance presents a challenge. A special test setup (Figure
40) was developed for this purpose. T he input signal was ob-
tained from a resonant reed switch pulse generator, available
from T ektronix as calibration Fixture No. 067-0608-00. When
open, the switch is simply 50
to ground and settling is purely
a passive pulse decay and inherently flat. T he low repetition rate
signal was captured on a digital oscilloscope after being ampli-
fied and clamped twice. T he selection of plug-in for the oscillo-
scope was made for minimum overload recovery.
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