TIMING CHARACTERISTICS1 (V DD <" />
參數(shù)資料
型號(hào): AD7824LNZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 10/16頁(yè)
文件大小: 0K
描述: IC ADC 8BIT LC2MOS 4CH HS 24DIP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 15
位數(shù): 8
采樣率(每秒): 100k
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 3
功率耗散(最大): 100mW
電壓電源: 單電源
工作溫度: 0°C ~ 70°C
安裝類(lèi)型: 通孔
封裝/外殼: 24-DIP(0.300",7.62mm)
供應(yīng)商設(shè)備封裝: 24-PDIP
包裝: 管件
輸入數(shù)目和類(lèi)型: 8 個(gè)單端,單極
AD7824/AD7828
REV. F
–3–
TIMING CHARACTERISTICS1 (V
DD = 5 V; VREF(+) = 5 V; VREF(–) = GND = 0 V, unless otherwise noted.)
Limit at 25 C
Limit at TMIN, TMAX
Parameter
(All Grades)
(K, L, B, C Grades)
(T, U Grades)
Unit
Conditions/Comments
tCSS
00
0
ns min
CS to RD Setup Time
tCSH
00
0
ns min
CS to RD Hold Time
tAS
00
0
ns min
Multiplexer Address Setup Time
tAH
30
35
40
ns min
Multiplexer Address Hold Time
tRDY
2
40
60
ns max
CS to RDY Delay. Pull-Up
Resistor 5 k
.
tCRD
2.0
2.4
2.8
s max
Conversion Time, Mode 0
tACC1
3
85
110
120
ns max
Data Access Time after
RD
tACC2
3
50
60
70
ns max
Data Access Time after
INT, Mode 0
tlNTH
2
40
65
70
ns typ
RD to INT Delay
75
100
ns max
tDH
4
60
70
ns max
Data Hold Time
tP
500
600
ns min
Delay Time between Conversions
tRD
60
80
ns min
Read Pulsewidth, Mode 1
600
500
400
ns max
NOTES
1Sample tested at 25
°C to ensure compliance. All input control signals are specified with t
RISE = tFALL = 20 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2C
L = 50 pF.
3Measured with load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
4Defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
Specifications subject to change without notice.
Test Circuits
DBN
3k
100pF
DGND
a. High-Z to VOH
DBN
3k
100pF
DGND
5V
b. High-Z to VOL
Figure 1. Load Circuits for Data Access Time Test
DBN
3k
10pF
DGND
a. VOH to High-Z
DBN
3k
10pF
DGND
5V
b. VOL to High-Z
Figure 2. Load Circuits for Data Hold Time Test
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