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參數(shù)資料
| 型號： | AD781* |
| 元件分類： | 取樣保持放大器 |
| 英文描述： | Complete 700 ns Sample-and-Hold Amplifier |
| 中文描述： | 完成700納秒采樣保持放大器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 153K |
AD781
REV. A
–6–
DY NAMIC PE RFORMANCE
T he AD781 is compatible with 12-bit A-to-D converters in
terms of both accuracy and speed. T he fast acquisition time, fast
hold settling time and good output drive capability allow the
AD781 to be used with high speed, high resolution A-to-D
converters like the AD674 and AD7672. T he AD781’s fast
acquisition time provides high throughput rates for multichannel
data acquisition systems. T ypically, the sample and hold can
acquire a 10 V step in less than 600 ns. Figure 1 shows the
settling accuracy as a function of acquisition time.
0.08
0.06
0.04
0.02
0
0
250
500
750
1000
ACQUISITION TIME – ns
V
O
Figure 1. V
OUT
Settling vs. Acquisition Time
T he hold settling determines the required time, after the hold
command is given, for the output to settle to its final specified
accuracy. T he typical settling behavior of the AD781 is shown
in Figure 2. T he settling time of the AD781 is sufficiently fast to
allow the SHA, in most cases, to directly drive an A-to-D
converter without the need for an added “start convert” delay.
Figure 2. Typical AD781 Hold Mode
HOLD MODE OFFSE T
T he dc accuracy of the AD781 is determined primarily by the
hold mode offset. T he hold mode offset refers to the difference
between the final held output voltage and the input signal at the
time the hold command is given. T he hold mode offset arises
from a voltage error introduced onto the hold capacitor by
charge injection of the internal switches. T he nominal hold
mode offset is specified for a 0 V input condition. Over the
input range of –5 V to +5 V, the AD781 is also characterized for
an effective gain error and nonlinearity of the held value, as
shown in Figure 3. As indicated by the AD781 specifications,
the hold mode offset is very stable over temperature.
NONLINEARITY
GAIN ERROR
(V HOLD – V ), mV
V , VOLTS
–4
–5
–3
–2
–1
1
2
3
4
+5
+1
HOLD MODE OFFSET
–1
Figure 3. Hold Mode Offset, Gain Error and Nonlinearity
For applications where it is important to obtain zero offset, the
hold mode offset may be nulled externally at the input to the
A-to-D converter. Adjustment of the offset may be accom-
plished through the A-to-D itself or by an external amplifier
with offset nulling capability (e.g., AD711). T he offset will
change less than 0.5 mV over the specified temperature range.
SUPPLY DE COUPLING AND GROUNDING
C ONSIDE RAT IONS
As with any high speed, high resolution data acquisition system,
the power supplies should be well regulated and free from exces-
sive high frequency noise (ripple). T he supply connection to the
AD781 should also be capable of delivering transient currents to
the device. T o achieve the specified accuracy and dynamic per-
formance, decoupling capacitors must be placed directly at both
the positive and negative supply pins to common. Ceramic type
0.1
μ
F capacitors should be connected from V
CC
and V
EE
to
common.
ANALOG
P.S.
DIGITAL
P.S.
+12V
C
–12V
C
+5V
0.1μF
0.1μF
1μF
1μF
1μF
AD781
DIGITAL
DATA
OUTPUT
SIGNAL GROUND
7
9
11
1
15
AD674
INPUTS
+
Figure 4. Basic Grounding and Decoupling Diagram
T he AD781 does not provide separate analog and digital ground
leads as is the case with most A-to-D converters. T he common
pin is the single ground terminal for the device. It is the refer-
ence point for the sampled input voltage and the held output
voltage and also the digital ground return path. T he common
pin should be connected to the reference (analog) ground of the
A-to-D converter with a separate ground lead. Since the analog
and digital grounds in the AD781 are connected internally, the
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