參數(shù)資料
| 型號： | SC16C650BIB48,128 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 2/48頁 |
| 文件大小： | 0K |
| 描述： | IC UART SOT313-2 |
| 標準包裝： | 2,000 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935274391128 SC16C650BIB48-F SC16C650BIB48-F-ND |
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SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
10 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
6.3 Hardware ow control
When automatic hardware ow control is enabled, the SC16C650B monitors the CTS pin
for a remote buffer overow indication and controls the RTS pin for local buffer overows.
Automatic hardware ow control is selected by setting EFR[6] (RTS) and EFR[7] (CTS) to
a logic 1. If CTS changes from a logic 0 to a logic 1 indicating a ow control request,
ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C650B will suspend
TX transmissions as soon as the stop bit of the character in process is shifted out.
Transmission is resumed after the CTS input returns to a logic 0, indicating more data may
be sent.
With the auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1 (RTS
off), until the receive FIFO reaches the next trigger level. However, the RTS pin will return
to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below the
programmed trigger level. However, under the above described conditions, the
SC16C650B will continue to accept data until the receive FIFO is full.
6.4 Software ow control
When software ow control is enabled, the SC16C650B compares one or two sequential
receive data characters with the programmed Xon or Xoff character value(s). If received
character(s) match the programmed Xoff values, the SC16C650B will halt transmission
(TX) as soon as the current character(s) has completed transmission. When a match
occurs, the receive ready (if enabled via Xoff IER[5]) ags will be set and the interrupt
output pin (if receive interrupt is enabled) will be activated. Following a suspension due to
a match of the Xoff characters’ values, the SC16C650B will monitor the receive data
stream for a match to the Xon1, Xon2 character value(s). If a match is found, the
SC16C650B will resume operation and clear the ags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit ow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software ow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the SC16C650B
compares two consecutive receive characters with two software ow control 8-bit values
(Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above
described ow control mechanisms, ow control characters are not placed (stacked) in the
user accessible RX data buffer or FIFO. When using a software ow control the Xon/Xoff
characters cannot be used for data transfer.
Table 4.
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
88
8
0
16
7
24
15
28
23
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