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參數(shù)資料
| 型號： | SC16C650BIB48,128 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART SOT313-2 |
| 標準包裝： | 2,000 |
| 通道數(shù)： | 1，UART |
| FIFO's： | 32 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 935274391128 SC16C650BIB48-F SC16C650BIB48-F-ND |
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SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
21 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.4 Interrupt Status Register (ISR)
The SC16C650B provides six levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table 13 “Interrupt source” shows the data values (bits 0:5) for the six prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 13.
Interrupt source
Priority
level
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
1
0
LSR (receiver Line Status
Register)
2
0
1
0
RXRDY (Received Data Ready)
2
0
1
0
RXRDY (Receive Data time-out)
3
0
1
0
TXRDY (Transmitter Holding
Register Empty)
4
0
MSR (Modem Status Register)
5
0
1
0
RXRDY (Received Xoff signal) /
Special character
6
1
0
CTS, RTS change of state
Table 14.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not being
used. They are set to a logic 1 when the FIFOs are enabled.
logic 0 or cleared = default condition
5:4
ISR[5:4]
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a logic 1.
ISR[4] indicates that matching Xoff character(s) have been detected. ISR[5]
indicates that CTS, RTS have been generated. Note that once set to a
logic 1, the ISR[4] bit will stay a logic 1 until Xon character(s) are received.
logic 0 or cleared = default condition
3:1
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending interrupt at
interrupt priority levels 1, 2, and 3 (see Table 13).
logic 0 or cleared = default condition
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used as a
pointer to the appropriate interrupt service routine.
logic 1 = no interrupt pending (normal default condition)
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