Table 2-40 A54SX72A Timing Characteristics (Worst-Case Commercial Conditions V
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鍨嬭櫉(h脿o)锛� A54SX32A-PQ208I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 78/108闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA SX 48K GATES 208-PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� SX-A
LAB/CLB鏁�(sh霉)锛� 2880
杓稿叆/杓稿嚭鏁�(sh霉)锛� 174
闁€鏁�(sh霉)锛� 48000
闆绘簮闆诲锛� 2.25 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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SX-A Family FPGAs
v5.3
2-51
Table 2-40 A54SX72A Timing Characteristics
(Worst-Case Commercial Conditions VCCA = 2.25 V, VCCI = 3.0 V, TJ = 70掳C)
Parameter
Description
鈥�3 Speed1
鈥�2 Speed
鈥�1 Speed
Std. Speed
鈥揊 Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
3.3 V PCI Output Module Timing2
tDLH
Data-to-Pad Low to High
2.3
2.7
3.0
3.6
5.0
ns
tDHL
Data-to-Pad High to Low
2.5
2.9
3.2
3.8
5.3
ns
tENZL
Enable-to-Pad, Z to L
1.4
1.7
1.9
2.2
3.1
ns
tENZH
Enable-to-Pad, Z to H
2.3
2.7
3.0
3.6
5.0
ns
tENLZ
Enable-to-Pad, L to Z
2.5
2.8
3.2
3.8
5.3
ns
tENHZ
Enable-to-Pad, H to Z
2.5
2.9
3.2
3.8
5.3
ns
dTLH
3
Delta Low to High
0.025
0.03
0.04
0.045
ns/pF
dTHL
3
Delta High to Low
0.015
0.025
ns/pF
3.3 V LVTTL Output Module Timing4
tDLH
Data-to-Pad Low to High
3.2
3.7
4.2
5.0
6.9
ns
tDHL
Data-to-Pad High to Low
3.2
3.7
4.2
4.9
6.9
ns
tDHLS
Data-to-Pad High to Low鈥攍ow slew
10.3
11.9
13.5
15.8
22.2
ns
tENZL
Enable-to-Pad, Z to L
2.2
2.6
2.9
3.4
4.8
ns
tENZLS
Enable-to-Pad, Z to L鈥攍ow slew
15.8
18.9
21.3
25.4
34.9
ns
tENZH
Enable-to-Pad, Z to H
3.2
3.7
4.2
5.0
6.9
ns
tENLZ
Enable-to-Pad, L to Z
2.9
3.3
3.7
4.4
6.2
ns
tENHZ
Enable-to-Pad, H to Z
3.2
3.7
4.2
4.9
6.9
ns
dTLH
3
Delta Low to High
0.025
0.03
0.04
0.045
ns/pF
dTHL
3
Delta High to Low
0.015
0.025
ns/pF
dTHLS
3
Delta High to Low鈥攍ow slew
0.053
0.067
0.073
0.107
ns/pF
Notes:
1. All 鈥�3 speed grades have been discontinued.
2. Delays based on 10 pF loading and 25
惟 resistance.
3. To obtain the slew rate, substitute the appropriate Delta value, load capacitance, and the VCCI value into the following equation:
Slew Rate [V/ns] = (0.1*VCCI 鈥� 0.9*VCCI)/ (Cload * dT[LH|HL|HLS])
where Cload is the load capacitance driven by the I/O in pF
dT[LH|HL|HLS] is the worst case delta value from the datasheet in ns/pF.
4. Delays based on 35 pF loading.
鐩搁棞(gu膩n)PDF璩囨枡
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