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鍨嬭櫉锛� A3PN250-Z2VQG100
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 61/114闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 250K GATES 100-VQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASIC3 nano
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 68
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-TQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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ProASIC3 nano DC and Switching Characteristics
2-36
Revision 11
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-50 Minimum and Maximum DC Input and Output Levels
1.5 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH IOSL IOSH IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3 A4 A4
2 mA
鈥�0.3 0.35 * VCCI 0.65 * VCCI
3.6
0.25 * VCCI 0.75 * VCCI 2
2
13
16
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100掳C junction temperature) and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-9 AC Loading
Table 2-51 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring Point* (V)
CLOAD (pF)
0
1.5
0.75
10
Notes:
1. Measuring point = Vtrip. See Table 2-16 on page 2-17 for a complete table of trip points.
2. Capacitive Load for A3PN060, A3PN125, and A3PN250 is 35 pF.
Test Point
Enable Path
Datapath
35 pF
R = 1 k
R to VCCI for tLZ / tZL / tZLS
R to GND for tHZ / tZH / tZHS
35 pF for tZH / tZHS / tZL / tZLS
35 pF for tHZ / tLZ
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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