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參數(shù)資料
| 型號： | ES29BDS400E-90RWCI |
| 廠商： | 優(yōu)先(蘇州)半導(dǎo)體有限公司 |
| 英文描述： | 4Mbit(512Kx 8/256K x 16) CMOS 3.0 Volt-only, Boot Sector Flash Memory |
| 中文描述： | 的4Mb（512Kx 8/256K × 16），3.0伏的CMOS只，引導(dǎo)扇區(qū)閃存 |
| 文件頁數(shù)： | 38/51頁 |
| 文件大?。?/td> | 697K |
| 代理商： | ES29BDS400E-90RWCI |
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ES I
43
Rev.0B January 5, 2006
ES29LV400E
Excel Semiconductor inc.
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.7
10
sec
Excludes 00h programming prior to
erasure (Note 4)
Chip Erase Time
8
sec
Byte Program Time
6
150
us
Exclude system level overhead (Note 5)
Word Program Time
8
210
us
Chip Program Time (Note 3)
Byte Mode
3.1
9.3
sec
Word Mode
2.1
6.3
Notes:
1. Typical program and erase times assume the following conditions: 25oC, 3.0V Vcc, 10,000 cycles. Additionally, programming
typicals assume checkerboard pattern.
2. Under worst case conditions of 90oC, Vcc = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two-or-four-bus-cycle sequence for the program command. See
Table 5 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles.
Description
Min
Max
Input voltage with respect to Vss on all pins except I/O pins (including A9, OE#, and RESET#)
- 1.0V
12.5 V
Input voltage with respect to Vss on all I/O pins
- 1.0V
Vcc + 1.0 V
Vcc Current
- 100 mA
+100 mA
Note: Includes all pins except Vcc. Test conditions: Vcc = 3.0 V, one pin at a time
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
TSOP
6
7.5
pF
FBGA
4.2
5.0
pF
COUT
Output Capacitance
VOUT = 0
TSOP
8.5
12
pF
FBGA
5.4
6.5
pF
CIN2
Control Pin Capacitance
VIN = 0
TSOP
7.5
9
pF
FBGA
3.9
4.7
pF
Table 17. LATCHUP CHARACTERISTICS
Table 18. TSOP, SO, AND BGA PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25oC, f=1.0MHz.
Parameter Description
Test conditions
Min
Unit
Minimum Pattern Data Retention Time
150oC
10
Years
125oC
20
Years
Table 19. DATA RETENTION
Table 16. ERASE AND PROGRAMMING PERFORMANCE
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