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參數(shù)資料
| 型號： | 935271535112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256 X 8 EEPROM, 8 I/O, PIA-GENERAL PURPOSE, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 935271535112 |
Philips Semiconductors
Product data
PCA9501
8-bit I2C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
2002 Sep 27
11
Acknowledge (see Figure 18)
The number of data bytes transferred between the start and the stop
conditions from transmitter to receiver is not limited. Each byte of
eight bits is followed by one acknowledge bit. The acknowledge bit
is a HIGH level put on the bus by the transmitter whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge
after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse, set-up and hold times must be
taken into account.
A master receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has been
clocked out of the slave. In this event the transmitter must leave the
data line HIGH to enable the master to generate a stop condition.
S
9
8
2
1
SW00545
DATA OUTPUT
BY TRANSMITTER
DATA OUTPUT
BY RECEIVER
SCL FROM
MASTER
ACKNOWLEDGE
NOT ACKNOWLEDGE
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
CONDITION
Figure 18. Acknowledgment on the I2C-bus
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