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參數(shù)資料
| 型號： | 935271535112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256 X 8 EEPROM, 8 I/O, PIA-GENERAL PURPOSE, PDSO20 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-360-1, TSSOP-20 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 125K |
| 代理商： | 935271535112 |
Philips Semiconductors
Product data
PCA9501
8-bit I2C and SMBus I/O port with interrupt,
2-kbit EEPROM and 6 address pins
2002 Sep 27
10
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between different ICs
or modules. The two lines are a serial data line (SDA) and a serial
clock line (SCL). Both lines must be connected to a positive supply
via a pull-up resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not busy.
Bit transfer
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock
pulse as changes in the data line at this time will be interpreted as
control signals (See Figure 15).
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
HIGH-to-LOW transition of the data line, while the clock is HIGH is
defined as the start condition (S). A LOW-to-HIGH transition of the
data line while the clock is HIGH is defined as the stop condition (P)
(see Figure 16).
System configuration
A device generating a message is a “transmitter”, a device receiving
is the “receiver”. The device that controls the message is the
“master” and the devices which are controlled by the master are the
“slaves” (see Figure 17).
SDA
SCL
SW00542
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
Figure 15. Bit transfer
SDA
SCL
P
SDA
SCL
S
SW00543
START CONDITION
STOP CONDITION
Figure 16. Definition of start and stop conditions
SDA
SCL
SW00544
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
Figure 17. System configuration
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