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參數(shù)資料
| 型號： | 935271534118 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 256 X 8 EEPROM, 8 I/O, PIA-GENERAL PURPOSE, PDSO16 |
| 封裝： | 4.40 MM, PLASTIC, MO-153, SOT-403-1, TSSOP-16 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 131K |
| 代理商： | 935271534118 |
Philips Semiconductors
Product data
PCA9500
8-bit I2C and SMBus I/O port with 2-kbit EEPROM
2002 Sep 27
7
MEMORY OPERATIONS
Write operations
Write operations require an additional address field to indicate the
memory address location to be written. The address field is eight
bits long, providing access to any one of the 256 words of memory.
There are two types of write operations, byte write and page write.
Write operation is possible when WC control pin put at a low logic
level (0). When this control signal is set at 1, write operation is not
possible and data in the memory is protected.
Byte Write and Page Write explained below assume that Write
Control pin (WC) is set to 0.
Byte Write (see Figure 8)
To perform a byte write the start condition is followed by the memory
slave address and the R/W bit set to 0. The PCA9500 will respond
with an acknowledge and then consider the next eight bits sent as
the word address and the eight bits after the word address as the
data. The PCA9500 will issue an acknowledge after the receipt of
both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle
to the non-volatile memory. Only write and read operations to the
Quasi-bidirectional I/O are allowed during the internal write cycle.
Page Write (see Figure 9)
A page write is initiated in the same way as the byte write. If after
sending the first word of data, the stop condition is not received the
PCA9500 considers subsequent words as data. After each data
word the PCA9500 responds with an acknowledge and the two least
significant bits of the memory address field are incremented. Should
the master not send a stop condition after four data words the
address counter will return to its initial value and overwrite the data
previously written. After the receipt of the stop condition the inputs
will behave as with the byte write during the internal write cycle.
SW02036
STOP CONDITION.
WRITE TO THE
MEMORY IS
PERFORMED
ACKNOWLEDGE
FROM SLAVE
S
1
0
1
0
A2
A1
A0
0
A
SDA
ACKNOWLEDGE
FROM SLAVE
R/W
START CONDITION
ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA
P
DATA
Figure 8. Byte write
SW02037
ACKNOWLEDGE
FROM SLAVE
S
1
0
1
0
A2 A1 A0
0
A
SDA
ACKNOWLEDGE
FROM SLAVE
R/W
START CONDITION
ACKNOWLEDGE
FROM SLAVE
SLAVE ADDRESS (MEMORY)
WORD ADDRESS
DATA TO MEMORY
DATA n
A
P
DATA n + 3
STOP CONDITION.
WRITE TO THE MEMORY
IS PERFORMED
DATA TO MEMORY
Figure 9. Page Write
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