參數(shù)資料
型號(hào)： 935269846112
廠商： NXP SEMICONDUCTORS
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： 6.10 MM, PLASTIC, MO-153, SOT-362-1, TSSOP-48
文件頁(yè)數(shù)： 14/14頁(yè)
文件大小： 89K
代理商： 935269846112
Philips Semiconductors
Product data
PCK2022RA
CK00 (100/133 MHz) spread spectrum differential
system clock generator
2001 Jun 12
9
REF clock output
Tamb = 0 to +70 °C; lump capacitance test load = 20 pF
LIMITS
SYMBOL
PARAMETER
48 MHz MODE
UNITS
NOTES
MIN
MAX
f
Frequency, actual
14.318
MHz
17, 20
tHKL
REFCLK LOW time
30
37
ns
20
tHKH
REFCLK HIGH time
30
37
ns
20
tJITTER
Cycle-to-cycle jitter
—
300
ps
18, 20
DUTY CYCLE
Output duty cycle
45
55
%
18, 20
REFER TO NOTES ON PAGE 9.
All outputs
Tamb = 0 to +70 °C
LIMITS
SYMBOL
PARAMETER
133 MHz MODE
100 MHz MODE
UNITS
NOTES
MIN
MAX
MIN
MAX
tPZL, tPZH
Output enable delay (all outputs)
1.0
10.0
1.0
10.0
ns
20
tPZL, tPZH
Output disable delay (all outputs)
1.0
10.0
1.0
10.0
ns
20
tSTABLE
All clock stabilization from power-up
—
3
—
3
ms
7, 20
REFER TO NOTES ON PAGE 9.
Group offset limits
GROUP
OFFSET
MEASUREMENT LOADS
(LUMPED)
MEASUREMENT POINTS
NOTES
Host to IOCLK
1.5 – 3.5 ns
Host leads
IOCLK @ 30 pF
Host @ Cross point
IOCLK @ 1.5 V
19, 20
NOTES TO THE AC TABLES:
1. Output drivers must have monotonic rise/fall times through the specified VOL/VOH levels.
2. Period, jitter, offset, and skew measured on rising edge at 1.5 V for 3.3 V clocks.
3. The IOCLK clock is the Host clock divided by 4 in 33 MHz mode and divided by 2 in 66 MHz mode at Host = 133 MHz.
IOCLK clock is the Host clock divided by 3 in 33 MHz and divided by 2/3 in 66 MHz mode at Host = 100 MHz.
4. Frequency accuracy of 48 MHz must be +167 ppm to match USB default.
5. tHKH is measured at 2.4 V for 3.3 V outputs, as shown in Figure 7.
6. tHKL is measured at 0.4 V for all outputs as shown in Figure 7.
7. the time is specified from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency output is stable
and operating within specification.
8. tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.
9. The average period over any 1
s period of time must be greater than the minimum specified period.
10. Calculated at minimum edge rate (1 V/ns) to guarantee 45–55% duty cycle. Pulse width is required to be wider at faster edge rate to ensure
duty specification is met.
11. Test load is RS = 33.2 , RP = 49.9 .
12. Must be guaranteed in a realistic system environment.
13. Configured for VOH = 0.71 V in a 50 environment.
14. Measured at crossing points.
15. Measured at 20% to 80%.
16. Determined as a fraction of 2*(tRP – tRN) / (tRP + tRN), where tRP is a rising edge, and tRN is an intersecting falling edge.
17. Frequency generated by crystal oscillator
18. Voltage measure point (VM = 1.5 V). VDD = 3.3 V.
19. All offsets are to be measured at rising edges.
20. Parameters are guaranteed by design.
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