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參數(shù)資料
| 型號(hào)： | 935267470125 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 門(mén)電路 |
| 英文描述： | AHC SERIES, 1-INPUT NON-INVERT GATE, PDSO5 |
| 封裝： | PLASTIC, SOT-353, SC-88A, 5 PIN |
| 文件頁(yè)數(shù)： | 9/16頁(yè) |
| 文件大小： | 77K |
| 代理商： | 935267470125 |
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2002 Oct 02
2
Philips Semiconductors
Product specication
Buffer with open-drain output
74AHC1G07; 74AHCT1G07
FEATURES
High noise immunity
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
Low power dissipation
SOT353 and SOT753 packages
Output capability standard (open-drain)
Specified from 40 to +125 °C.
DESCRIPTION
The 74AHC1G/AHCT1G07 is a high-speed Si-gate CMOS
device.
The 74AHC1G/AHCT1G07 provides the non-inverting
buffer.
The output of the 74AHC1G/AHCT1G07 devices is
open-drain and can be connected to other open-drain
outputs to implement active-LOW wired-OR or
active-HIGH wired-AND functions. For digital operation
this device must have a pull-up resistor to establish a logic
HIGH-level.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf ≤ 3.0 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi +(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC1G
AHCT1G
tPZL
propagation delay A to Y
CL = 15 pF; VCC = 5 V
2.5
2.8
ns
tPLZ
propagation delay A to Y
CL = 15 pF; VCC = 5 V
4.2
3.9
ns
CI
input capacitance
1.5
pF
CPD
power dissipation capacitance
CL = 50 pF; f = 1 MHz; notes 1 and 2
5
6.5
pF
INPUT
OUTPUT
AY
LL
HZ
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