參數(shù)資料
型號(hào)： 935254340118
廠商： NXP SEMICONDUCTORS
元件分類： 總線收發(fā)器
英文描述： ALVC/VCX/A SERIES, 16 1-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
文件頁(yè)數(shù)： 11/18頁(yè)
文件大?。?/td> 129K
代理商： 935254340118
1999 Sep 20
2
Philips Semiconductors
Product specication
16-bit transceiver with dual enable; 3-state
74ALVCH16623
FEATURES
Complies with JEDEC standard
no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
MULTIBYTE flow-through
standard pin-out architecture
All data inputs have bus hold
circuitry
Output drive capability 50
transmission lines at 85
°C
Current drive ±24 mA at 3.0 V.
DESCRIPTION
The 74ALVCH16623 is a high-performance, low-power, low-voltage, Si-gate
CMOS device, superior to most advanced CMOS compatible TTL families.
The 74ALVCH16623 is a 16-bit transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions.
This 16-bit bus transceiver is designed for asynchronous two-way
communication between data buses. The control function implementation
allows maximum flexibility in timing. This device allows data transmission from
the A bus to the B bus or from the B bus to the A bus, depending upon the logic
levels at the enable inputs (nOEAB,nOEBA). The enable inputs can be used to
disable the device so that the buses are effectively isolated. The dual enable
function configuration gives this transceiver the capability to store data by
simultaneous enabling of nOEAB and nOEBA. Each output reinforces its input in
this transceiver configuration. Thus, when all control inputs are enabled and all
other data sources to the four sets of the bus lines are at high-impedance
OFF-state, all sets of bus lines will remain at their last states. The 8-bit codes
appearing on the two double sets of buses will be complementary. This device
can be used as two 8-bit transceivers or one 16-bit transceiver.
To ensure the high-impedance state during power-on or power-down, OEBA
should be tied to VCC through a pull-up resistor and OEAB should be tied to GND
through a pull-down resistor; the minimum value of the resistor is determined
by the current-sinking/current-sourcing capability of the driver.
Active bus hold circuitry is provided to hold unused or floating data inputs at a
valid logic level.
QUICK REFERENCE DATA
Ground = 0; Tamb =25 °C; tr =tf = 2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD =CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
CL = output load capacitance in pF;
fo = output frequency in MHz;
VCC = supply voltage in Volts;
Σ (CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
propagation delay nAn,nBn to nBn,nAn
CL = 30 pF; VCC = 2.5 V
2.0
ns
CL = 50 pF; VCC = 3.3 V
1.9
ns
CI/O
input/output capacitance
10.0
pF
CI
input capacitance
3.0
pF
CPD
power dissipation capacitance per buffer notes 1 and 2
outputs enabled
35
pF
outputs disabled
5
pF
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