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參數(shù)資料
| 型號： | 9250YF-27LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.25 INCH PITCH, ROHS COMPLIANT, MO-118, TSSOP-56 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大?。?/td> | 195K |
| 代理商： | 9250YF-27LF-T |
IDTTM
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
0395F—01/25/10
ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
3
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#
D
PK
L
C
U
P
CM
A
R
D
SC
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P
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6
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c
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Os
O
C
V
0W
O
LW
O
LW
O
LW
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LW
O
LW
O
LF
F
OF
F
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1N
ON
O
5
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