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參數(shù)資料
| 型號： | 74HCT75D |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 鎖存器 |
| 英文描述： | Quad bistable transparent latch |
| 中文描述： | HCT SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 57K |
| 代理商： | 74HCT75D |
December 1990
2
Philips Semiconductors
Product specification
Quad bistable transparent latch
74HC/HCT75
FEATURES
Complementary Q and Q outputs
V
CC
and GND on the centre pins
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
1-2
and LE
3-4
). When LE
n-n
is
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
n-n
is HIGH (transparent). The data on the nD inputs
one set-up time prior to the HIGH-to-LOW transition of the
LE
n-n
will be stored in the latches. The latched outputs
remain stable as long as the LE
n-n
is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
= 6 ns
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
2.
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
t
PHL
/ t
PLH
propagation delay
nD to nQ, nQ
LE
n-n
to nQ, nQ
input capacitance
power dissipation capacitance per latch
C
L
= 15 pF; V
CC
= 5 V
11
11
3.5
42
12
11
3.5
42
ns
ns
pF
pF
C
I
C
PD
notes 1 and 2
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