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參數(shù)資料
| 型號： | 74HC4510 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 通用總線功能 |
| 英文描述： | BCD up/down counter |
| 中文描述： | BCD碼向上/向下計數(shù)器 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 102K |
| 代理商： | 74HC4510 |
December 1990
9
Philips Semiconductors
Product specication
BCD up/down counter
74HC/HCT4510
trem
removal time
MR to CP
23
13
29
35
ns
4.5
Fig.10
trem
removal time
PL to CP
17
10
21
26
ns
4.5
Fig.10
tsu
set-up time
UP/DN to CP
20
12
25
30
ns
4.5
Fig.8
tsu
set-up time
CE to CP
20
6
25
30
ns
4.5
Fig.8
tsu
set-up time
Dn to PL
20
6
25
30
ns
4.5
Fig.11
th
hold time
CE to CP
5
0
5
ns
4.5
Fig.8
th
hold time
Dn to PL
5
0
5
ns
4.5
Fig.11
th
hold time
UP/DN to CP
0
5
0
ns
4.5
Fig.8
fmax
maximum clock pulse
frequency
30
53
24
20
MHz
4.5
Fig.7
SYMBOL
PARAMETER
Tamb (°C)
UNIT
TEST CONDITIONS
74HCT
VCC
(V)
WAVEFORMS
+25
40 to +85
40 to +125
min.
typ.
max.
min.
max.
min.
max.
AC WAVEFORMS
Fig.7
Waveforms showing the clock (CP) to
output (Qn) and terminal count (TC)
propagation delays, the clock pulse width
and the maximum clock pulse frequency.
(1)
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the set-up and hold
times from count enable (CE) and
up/down (UP/DN) control inputs to the
clock pulse (CP), the propagation delays
from UP/DN, CE to TC.
(1)
HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
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