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參數(shù)資料
| 型號： | 71256T36-10 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | 256K x 18 Synchronous-Pipelined Cache Tag RAM |
| 中文描述： | 256 × 18的同步高速緩存標(biāo)記內(nèi)存流水線 |
| 文件頁數(shù)： | 4/24頁 |
| 文件大?。?/td> | 244K |
| 代理商： | 71256T36-10 |
CY7C1359A/GVT71256T18
Document #: 38-05120 Rev. **
Page 4 of 24
Pin Descriptions
BGA Pins
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
2T, 3T, 5T, 6T
5L
3G
TQFP Pins
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49, 50
93
94
Name
A0
A1
A
Type
Input-
Description
Synchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
WEL
WEH
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. WEL controls DQ1
–
DQ9.
WEH controls DQ10
–
DQ18. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being
LOW.
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit
WRITE to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising edge
of CLK.
Clock: This signal registers the addresses, data, chip en-
ables, write control, and data input enable control input on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clock
’
s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
Chip Enable: This active LOW input is used to enable the
device.
Chip Enable: This active HIGH input is used to enable the
device.
Output Enable: This active LOW asynchronous input enables
the data output drivers.
Address Advance: This active LOW input is used to control
the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
Address Status Processor: This active LOW input, along with
CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated
depending upon write control inputs.
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
Data Input Enable: This active LOW input is used to control
the update of data input registers.
Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array, assum-
ing MOE being LOW. MATCH will be LOW if data do not
match.
4M
87
BWE
Input-
Synchronous
4H
88
GW
Input-
Synchronous
4K
89
CLK
Input-
Synchronous
4E
98
CE
Input-
Synchronous
Input-
Synchronous
input-
Synchronous
Input
6B
92
CE
2
2B
97
CE
2
4F
86
OE
4G
83
ADV
Input-
Synchronous
4A
84
ADSP
Input-
Synchronous
4B
85
ADSC
Input-
Synchronous
3R
31
MODE
Input-
Static
7T
64
ZZ
Input-
Asynchronous
7N
52
DEN
Input-
Synchronous
Output
6M
53
MATCH
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