參數(shù)資料
型號(hào)： 5962H0521404VXA
元件分類： XO, clock
英文描述： 200 MHz, OTHER CLOCK GENERATOR, CDFP48
封裝： CERAMIC, DFP-48
文件頁(yè)數(shù)： 6/22頁(yè)
文件大?。?/td> 174K
代理商： 5962H0521404VXA
14
8.0 AC INPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = VDDQn = +3.3V + 0.3V; TC = -55°C to +125°C) (Note 1)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019.
1. Reference Figure 11 for clock output loading circuit that is equivalent to the load circuit used for all AC testing. The input waveform used to test these parameters
is shown in Figure 9.
2. Supplied only as a design guideline, neither tested nor guaranteed.
3. When driving the UT7R995C with a crystal, the XTAL1 pin does not define maximum input rise/fall time.
4. Although the input reference frequencies are defined as-low-as 2MHz, the N and R dividers must be selected to ensure the PLL operates from 24MHz-50MHz when
FS = LOW, 48MHz-100MHz when FS = MID, and 96MHz-200MHz when FS = HIGH.
5. The UT7R995C is guaranteed by characterization for quartz crystal frequencies ranging from 2MHz to 48MHz. Contact the factory for support using quartz crystals
that oscillate above 48MHz.
6. For the UT7R995C only, this parameter is guaranteed by characterization, but not tested.
7. For the UT7R995C only, this parameter is guaranteed by characterization, but only tested for frequencies <100 MHz.
Symbol
Description
Condition
Min.
Max.
Unit
tR, tF
2, 3
Input rise/fall time
VIH(min)-VIL(max)
--
20
ns/V
tPWC
6
Input clock pulse
HIGH or LOW
2
--
ns
tXTAL
7
Input clock period
1÷FXTAL
5
500
ns
tDCIN
6
Input clock duty cycle
HIGH or LOW
10
90
%
fXTAL
4, 5, 7
Digital reference input frequency
FS = LOW; PD/DIV = HIGH
2
50
MHz
FS = LOW; PD/DIV = MID
4
100
MHz
FS = MID; PD/DIV = HIGH
4
100
MHz
FS = MID; PD/DIV = MID
8
200
MHz
FS = HIGH; PD/DIV = HIGH
8
200
MHz
FS = HIGH; PD/DIV = MID
16
200
MHz
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