參數(shù)資料
型號(hào)： 5962H0521404VXA
元件分類(lèi)： XO, clock
英文描述： 200 MHz, OTHER CLOCK GENERATOR, CDFP48
封裝： CERAMIC, DFP-48
文件頁(yè)數(shù)： 17/22頁(yè)
文件大?。?/td> 174K
代理商： 5962H0521404VXA
4
Notes:
1. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the nominal VCO operating frequency (fNOM)
at a given reference frequency (fXTAL) and the divider and feedback configuration. The user must select a configuration and a reference frequency that will generate
a VCO frequency that is within the range specified by FS pin. Please see Table 7.
1.2 Frequency Range and Skew Selection:
The PLL in the UT7R995/C operates within three nominal fre-
quency ranges. Depending upon the desired PLL operating fre-
quency, the user must define the state of the ternary FS control
pin. Table 7 defines the required FS selections based upon the
nominal PLL operating frequency ranges. Because the clock
outputs on Bank 1 and Bank 2 do not include a divider option,
they will always reflect the current frequency of the PLL. Ref-
erence the first column of equations in Table 6 to calculate the
value of fNOM for any given feedback clock.
Selectable output skew is in discrete increments of time unit
(tU). The value of tU is determined by the FS setting and the
PLL’s operating frequency (fNOM). Use the following equation
to calculate the time unit (tU):
The fNOM term, which is calculated with the help of Table 6,
must be compatible with the nominal frequency range selected
by the FS signal as defined in Table 7. The multiplication factor
(MF), also determined by FS, is shown in Table 8. The
UT7R995/C output skew steps have a typical accuracy of +/-
15% of the calculated time unit (tU).
After calculating the time unit (tU) based on the nominal PLL
frequency (fNOM) and multiplication factor (MF), the circuit
designer plans routing requirements of each clock output and its
respective destination receiver. With an understanding of signal
propagation delays through a conductive medium (see Table 9),
the designer specifies trace lengths which ensure a signal prop-
agation delay that is equal to one of the tU multiples show in Ta-
ble 10. For each output bank, the tU skew factors are selected
with the tri-level, bank-specific, nF[1:0] pins.
Table 6: Calculating Output Frequency Settings
Configuration
Output Frequency
Clock Output
Connected to FB
1Q[1:0] 1
and
2Q[1:0] 1
3Q[1:0]
4Q[1:0]
1Qn or 2Qn
(N/R) * fXTAL
(N/R) * (1/K) * fXTAL
(N/R) * (1/M) * fXTAL
3Qn
(N/R) * K * fXTAL
(N/R) * fXTAL
(N/R) * (K/M) * fXTAL
4Qn
(N/R) * M * fXTAL
(N/R) * (M/K) * fXTAL
(N/R) * fXTAL
Table 7: Frequency Range Select
FS
Nominal PLL Frequency Range (fNOM)
L
24 to 50 MHz
M
48 to 100MHz
H
96 to 200 MHz
MF)
*
NOM
(f
1
u
t
1.
Equation
=
Table 8: MF Calculation
FS
MF
fNOM examples that result
in a tU of 1.0ns
L
32
31.25 MHz
M
16
62.5 MHz
H
8
125 MHz
Table 9: Signal Propagation Delays in Various Media
Medium
Propagation
Delay (ps/inch)
Dielectric
Constant
Air (Radio Waves)
85
1.0
Coax. Cable (75% Velocity)
113
1.8
Coax. Cable (66% Velocity)
129
2.3
FR4 PCB, Outer Trace
140 - 180
2.8 - 4.5
FR4 PCB, Inner Trace
180
4.5
Alumina PCB, Inner Trace
240 - 270
8 - 10
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