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參數(shù)資料
| 型號： | 5962H0521402VXX |
| 元件分類： | XO, clock |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, CDFP48 |
| 封裝： | CERAMIC, DFP-48 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 174K |
| 代理商： | 5962H0521402VXX |
14
IN
DEVELOPMENT
Notes:
1. Reference Figure 11 for clock output loading circuit that is equivalent to the load circuit used for all AC testing.
2. Supplied as a design guideline. Neither guaranteed nor tested.
3. Test load = 40pF, terminated to VDD÷2. All outputs are equally loaded. See figure 11.
4. tPD is measured at 1.5V for VDD = 3.3V with XTAL1 rise/fall times of 1ns between 0.8V-2.0V.
5. tLOCK is the time that is required before outputs synchronize to XTAL1 as determined by the phase alignment between the XTAL1 and FB inputs. This specification
is valid with stable power supplies which are within normal operating limits.
6. Lock detector circuit will monitor the phase alignment between the XTAL1 and FB inputs. When the phase separation between these two inputs is greater than the
amount listed, then the LOCK pin will drop low signaling that the PLL is out of lock.
7. This parameter is guaranteed by measuring cycle-cycle jitter on 216, back-to-back clock cycles.
8. Guaranteed by characterization, but not tested.
tPD0
4, 8
XTAL1 to FB
propagation delay
VDD = VDDQn = +3.3V; TC = Room Temperature
-250
+250
ps
tODCV
Output duty cycle
fout < 100 MHz, measured at VDD÷2
48
52
%
fout > 100 MHz, measured at VDD÷2
45
55
%
tPWH
Output high time
deviation from 50%
Measured at 2.0V; VDDQn = +3.3V
--
1.5
ns
tPWL
Output low time
deviation from 50%
Measured at 0.8V; VDDQn = +3.3V
--
2.0
ns
tORISE
&
tOFALL
Output rise/fall time
Measured as transition time between
VOH = +1.7V and VOL = +0.7V
for VDDQn = +2.5V; CL = 40pF
PE/HD = HIGH
0.5
1.5
ns
PE/HD = MID
0.25
1.25
ns
Measured as transition time between
VOH = +2.0V and VOL = +0.8V
for VDDQn = +3.3V; CL = 40pF
PE/HD = HIGH
0.20
1.25
ns
PE/HD = MID
0.10
1.0
ns
tLOCK
5
PLL lock time
--
1
ms
tLOCKRES
2, 6
LOCK Pin Resolution
FS = LOW
1.6ns + 200ps typ.
ns
FS = MID
1.6ns + 200ps typ.
ns
FS = HIGH
800ps + 100ps typ.
ps
tCCJ
7
Cycle-cycle jitter
Divide by 1 output frequency,
FS = LOW, FB = divide by 12
--
100
ps
Divide by 1 output frequency
FS = MID or HIGH, FB = divide by 12
--
150
ps
Symbol
Description
Condition
Min.
Max.
Unit
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