參數(shù)資料
型號(hào)： 5962H0521402VXX
元件分類： XO, clock
英文描述： 200 MHz, OTHER CLOCK GENERATOR, CDFP48
封裝： CERAMIC, DFP-48
文件頁(yè)數(shù)： 3/23頁(yè)
文件大?。?/td> 174K
代理商： 5962H0521402VXX
11
IN
DEVELOPMENT
6.0 DC INPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = +3.3V + 0.3V; TC = -55°C to +125°C)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) +20%, -0%; VIL = VIL(max) +0%, -50%,
as specified herein for LVTTL and LVCMOS inputs. For 3-level inputs, VIH = VIHH(min) +50%, -0%; VIL = VILL(max) +0%, -50%; VIM = VIMM(nom) +0.1V, -0.1V.
Devices may be tested using any input voltage within the above specified range, but are guaranteed to VIH(min), VIL(max), VIHH(min), VILL(max), and VIMM(nom).
2. These inputs are normally wired to VDD, VSS, or left unconnected. Internal termination resistors bias unconnected inputs to VDD/2 + 0.3V. The 3-level inputs
include: TEST, PD/DIV, PE/HD, FS, nF[1:0], DS[1:0].
3. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
Symbol
Description
Conditions
Min.
Max.
Units
VIH
1
High-level input voltage
(XTAL1, FB and sOE inputs)
2.0
--
V
VIL
1
Low-level input voltage
(XTAL1, FB and sOE inputs)
--
0.8
V
VIHH
1,2
High-level input voltage
VDD - 0.6
--
V
VIMM
1,2
Mid-level input voltage
VDD÷2 - 0.3 VDD÷2 + 0.3
V
VILL
1,2
Low-level input voltage
--
0.6
V
IIL
Input leakage current
(XTAL1, FB and sOE inputs)
VIN = VDD or VSS; VDD = Max
-5
5
A
I3L
2
3-Level input DC current
HIGH, VIN = VDD
--
200
A
MID, VIN = VDD/2
-50
50
A
LOW, VIN = VSS
-200
--
A
IDDQ
Quiescent supply current
VDD = +3.0V; VDDQn = +3.0V; TEST & sOE = HIGH;
XTAL1, FB, FS, & PE/HD = LOW;
All other inputs are floated; Outputs are not loaded
--
4
mA
IDDPD
Power-down current
VDD = +3.0V; VDDQn = +3.0V; TEST & sOE = HIGH;
XTAL1, PD/DIV, FB, FS, & PE/HD = LOW;
All other inputs are floated; Outputs are not loaded
--
100
A
CIN-2L
3
Input pin capacitance
2-level inputs
f = 1MHz @ 0V; VDD = Max
8.5
pF
CIN-3L
3
Input pin capacitance
3-level inputs
f = 1MHz @ 0V; VDD = Max
15
pF
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