參數(shù)資料
型號(hào)： 5962F0521404VXA
元件分類(lèi)： XO, clock
英文描述： 200 MHz, OTHER CLOCK GENERATOR, CDFP48
封裝： CERAMIC, DFP-48
文件頁(yè)數(shù)： 7/22頁(yè)
文件大?。?/td> 174K
代理商： 5962F0521404VXA
15
9.0 AC OUTPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = +3.3V + 0.3V; TC = -55°C to +125°C) (For "W" screening, TC = -40°C to +125°C) (Note 1)
Symbol
Description
Condition
Min.
Max.
Unit
fOR
Output frequency range
VDDQn = +3.3V
6
200
MHz
VCOLR
VCO lock range
VDDQn = +3.3V
24
200
MHz
VCOLBW
2
VCO loop bandwidth
VDD = VDDQn = +3.3V; TC = Room Temperature
0.25
3.5
MHz
tSKEWPR
3, 8
Matched-pair skew
Skew between the earliest and the latest output transitions
within the same bank.
--
100
ps
tSKEW0
3, 8
Output-output skew
Skew between the earliest and the latest output transitions
among all outputs at 0tU.
--
200
ps
tSKEW1
3
Skew between the earliest and the latest output transitions
among all outputs for which the same phase delay has been
selected.
--
200
ps
tSKEW2
3
Skew between the nominal output rising edge to the
inverted output falling edge
--
500
ps
tSKEW3
3
Skew between non-inverted outputs running at different
frequencies.
--
500
ps
tSKEW4
3
Skew between nominal to inverted outputs running at
different frequencies.
--
600
ps
tSKEW5
3
Skew between nominal outputs at different power supply
levels.
--
650
ps
tPART
8
Part-part skew
Skew between the outputs of any two devices under
identical settings and conditions (VDDQn, VDD, temp, air
flow, frequency, etc).
--
450
ps
tPD0
4, 8
XTAL1 to FB
propagation delay
VDD = VDDQn = +3.3V; TC = Room Temperature
-250
+250
ps
tODCV
8
Output duty cycle
fout < 100 MHz, measured at VDD÷2
48
52
%
fout > 100 MHz, measured at VDD÷2
45
55
%
tPWH
Output high time
deviation from 50%
Measured at 2.0V; VDDQn = +3.3V
--
1.5
ns
tPWL
Output low time
deviation from 50%
Measured at 0.8V; VDDQn = +3.3V
--
2.0
ns
tORISE
8
&
tOFALL
Output rise/fall time
Measured as transition time between
VOH = +1.7V and VOL = +0.7V
for VDD = 3.0V; VDDQn = +2.25V;
CL = 40pF
PE/HD = HIGH
0.30
1.5
ns
PE/HD = MID
0.25
1.25
ns
Measured as transition time between
VOH = +2.0V and VOL = +0.8V
for VDD = 3.6V; VDDQn = +3.3V;
CL = 40pF
PE/HD = HIGH
0.20
1.25
ns
PE/HD = MID
0.10
1.0
ns
tLOCK
5
PLL lock time
--
0.5
ms
tLOCKRES
2, 6
LOCK Pin Resolution
FS = LOW
1.6ns + 200ps typ.
ns
FS = MID
1.6ns + 200ps typ.
ns
FS = HIGH
800ps + 100ps typ.
ps
相關(guān)PDF資料
PDF描述
5962H0521404VXA 200 MHz, OTHER CLOCK GENERATOR, CDFP48
514DCAXXXXXXBAG 250 MHz, OTHER CLOCK GENERATOR, PDSO6
514ECCXXXXXXAAGR 125 MHz, OTHER CLOCK GENERATOR, PDSO6
514KCAXXXXXXBAGR 250 MHz, OTHER CLOCK GENERATOR, PDSO6
514QBCXXXXXXBAGR 125 MHz, OTHER CLOCK GENERATOR, PDSO6
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