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參數(shù)資料
| 型號(hào)： | 5962F0521404VXA |
| 元件分類： | XO, clock |
| 英文描述： | 200 MHz, OTHER CLOCK GENERATOR, CDFP48 |
| 封裝： | CERAMIC, DFP-48 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 174K |
| 代理商： | 5962F0521404VXA |
11
6.0 DC INPUT ELECTRICAL CHARACTERISTICS (Pre- and Post-Radiation)*
(VDD = +3.3V + 0.3V; TC = -55°C to +125°C) (For "W" screening, TC = -40°C to +125°C)
Notes:
* Post-radiation performance guaranteed at 25
°C per MIL-STD-883 Method 1019, Condition A up to a TID level of 1.0E6 rad(Si).
1. These inputs are normally wired to VDD, VSS, or left unconnected. Internal termination resistors bias unconnected inputs to VDD/2 + 0.3V. The 3-level inputs
include: TEST, PD/DIV, PE/HD, FS, nF[1:0], DS[1:0].
2. Capacitance is measured for initial qualification and when design changes may affect the input/output capacitance. Capacitance is measured between the designated
terminal and VSS at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.
3. Pin FS is guaranteed by functional testing.
4. For pin FB, this specification is supplied as a design limit, but is neither guaranteed nor tested.
Symbol
Description
Conditions
Min.
Max.
Units
VIH
4
High-level input voltage
(XTAL1, FB and sOE inputs)
2.0
--
V
VIL
4
Low-level input voltage
(XTAL1, FB and sOE inputs)
--
0.8
V
VIHH
1, 3
High-level input voltage
VDD - 0.6
--
V
VIMM
1, 3
Mid-level input voltage
VDD÷2 - 0.3 VDD÷2 + 0.3
V
VILL
1, 3
Low-level input voltage
--
0.6
V
IIL
Input leakage current
(XTAL1, FB and sOE inputs)
VIN = VDD or VSS; VDD = Max
-5
5
μA
I3L
1
3-Level input DC current
HIGH, VIN = VDD
--
200
μA
MID, VIN = VDD/2
-50
50
μA
LOW, VIN = VSS
-200
--
μA
IDDPD
Power-down current
VDD = VDDQn = +3.0V;
TEST & sOE = HIGH;
XTAL1, PD/DIV, FB, FS, & PE/
HD = LOW;
All other inputs are floated;
Outputs are not loaded
TC = +25°C
--
100
μA
TC = +125°C
--
150
μA
TC = -55°C
--
4.5
mA
CIN-2L
2
Input pin capacitance
2-level inputs
f = 1MHz @ 0V; VDD = Max
8.5
pF
CIN-3L
2
Input pin capacitance
3-level inputs
f = 1MHz @ 0V; VDD = Max
15
pF
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