參數(shù)資料
型號(hào): 571SDAFREQDGR
廠商: SILICON LABORATORIES
元件分類(lèi): VCXO, clock
英文描述: VCXO, CLOCK, 10 MHz - 945 MHz, LVDS OUTPUT
封裝: ROHS COMPLIANT PACKAGE-8
文件頁(yè)數(shù): 24/26頁(yè)
文件大小: 315K
代理商: 571SDAFREQDGR
Si570/Si571
Rev. 0.31
7
Table 4. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
VDD – 1.25
V
VOD
swing (diff)
1.1
1.9
VPP
VSE
swing (single-ended)
0.55
0.95
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
VO
mid-level
VDD – 0.75
V
VOD
swing (diff)
0.70
0.95
1.20
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
VDD
V
VOL
IOL =32mA
0.4
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
350
ps
CMOS with CL =15pF
1
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V (diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
55
%
Notes:
1. 50
Ω to VDD – 2.0 V.
2. Rterm =100 Ω (differential).
3. CL =15pF
Table 5. CLK± Output Phase Jitter (Si570)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)*
for FOUT > 500 MHz
φ
J
12 kHz to 20 MHz (OC-48)
0.25
0.40
ps
50 kHz to 80 MHz (OC-192)
0.26
0.37
Phase Jitter (RMS)*
for FOUT of 125 to 500 MHz
φ
J
12 kHz to 20 MHz (OC-48)
0.36
0.50
ps
50 kHz to 20 MHz (OC-192)
0.34
0.42
*Note: Differential Modes: LVPECL/LVDS/CML. Refer to AN256 for further information.
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