參數(shù)資料
型號(hào)： 550JE100M000DGR
廠商： SILICON LABORATORIES
元件分類： VCXO, clock
英文描述： VCXO, CLOCK, 100 MHz, CMOS OUTPUT
封裝： ROHS COMPLIANT PACKAGE-6
文件頁(yè)數(shù)： 9/14頁(yè)
文件大?。?/td> 230K
代理商： 550JE100M000DGR
Si550
4
Rev. 0.6
Table 5. CLK± Output Phase Jitter
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Phase Jitter (RMS)1,2,3
for FOUT > 500 MHz
φ
J
Kv = 33 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.26
—
ps
Kv = 45 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.27
0.26
—
Kv = 90 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.32
0.26
—
Kv = 135 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.40
0.27
—
Kv = 180 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.49
0.28
—
Kv = 356 ppm/V
12 kHz to 20 MHz (OC-48)
50 kHz to 80 MHz (OC-192)
—
0.87
0.33
—
Notes:
1. Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
2. For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
3. See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply
rejection (PSR) advantage of Si55x versus SAW-based solutions.
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